Tadahiko Sugibayashi

发表

Shared Write-Selection Transistor Cell and Leakage-Replication Read Scheme for Large Capacity MRAM Macros

Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, 2009, IEICE Trans. Electron..

Architecture optimization of nanobridge-based field-programmable gate array and its evaluation

Toshitsugu Sakamoto, Hiromitsu Hada, Yukihide Tsuji, 2017 .

Demonstration of a Nonvolatile Processor Core Chip with Software-Controlled Three-Terminal MRAM Cells for Standby-Power Critical Applications

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2013 .

Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors

Nozomu Togawa, Masao Yanagisawa, Shinji Kimura, 2013, 2013 IEEE 10th International Conference on ASIC.

Writing Circuitry for Toggle MRAM to Screen Intermittent Failure Mode

Shuichi Tahara, Hiromitsu Hada, Takeshi Honda, 2007, IEICE Trans. Electron..

A 90nm 12ns 32Mb 2T1MTJ MRAM

Yuichi Ito, Hiroaki Honjo, Yosuke Kobayashi, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

High-speed simulator including accurate MTJ models for spintronics integrated circuit design

Hiroki Koike, Tetsuo Endoh, Takahiro Hanyu, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A 1-Gb DRAM for file applications

Toshiro Itani, Kunihiko Kasama, T. Murotani, 1995 .

A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

Low Power Memory Based Design Method of Constant Multipliers for Digital Filters

Masao Yanagisawa, Shinji Kimura, Tadahiko Sugibayashi, 2013 .

Soft-Delay-Error Evaluation in Content-Addressable Memory

Naoya Onizawa, Takahiro Hanyu, Shoun Matsunaga, 2014, 2014 IEEE 44th International Symposium on Multiple-Valued Logic.

Noncomplimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAM

Tadahiko Sugibayashi, Satoshi Utsugi, M. Hanyu, 1999 .

A 12-ns 8-Mbyte DRAM secondary cache for a 64-bit microprocessor

Tadahiko Sugibayashi, H. Hatayama, Isao Naritake, 1999 .

Programmable SpaceWire interface with atom switch: Components, short paper

Kazutoshi Wakabayashi, Akira Iwasaki, Toshitsugu Sakamoto, 2016, 2016 International SpaceWire Conference (SpaceWire).

A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond

Toshitsugu Sakamoto, Hiromitsu Hada, Yukihide Tsuji, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

ON-state retention of Atom Switch eNVM for IoT/AI Inference Solution

Munehiro Tada, Naoki Banno, Makoto Miyamura, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

NanoBridge-Based FPGA in High-Temperature Environments

Masayuki Inaba, Takuma Shirai, Toshitsugu Sakamoto, 2017, IEEE Micro.

High-speed MRAM for Embedding in SoC

Naoki Kasai, Nobuyuki Ishiwata, Tadahiko Sugibayashi, 2008 .

Energy Consumption Evaluation for Two-Level Cache with Non-Volatile Memory Targeting Mobile Processors

Masao Yanagisawa, Nozomu Togawa, Shinji Kimura, 2013 .

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Daisuke Suzuki, Tetsuo Endoh, Takahiro Hanyu, 2014, IEICE Electronics Express.

Pathway to Atomic-Switch Based Programmable Logic

Toshitsugu Sakamoto, Yukihide Tsuji, Munehiro Tada, 2020 .

A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs

Tadahiko Sugibayashi, Isao Naritake, Satoshi Utsugi, 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars

Masanori Hashimoto, Yukio Mitsuyama, Kazutoshi Wakabayashi, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Challenge of MOS/MTJ-hybrid nonvolatile logic-in-memory architecture in dark-silicon era

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2014, 2014 IEEE International Electron Devices Meeting.

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Kanbara, 2018, IEEE Embedded Systems Letters.

FA 14.6: A iGb DRAM for File Applications

Toshiro Itani, Kunihiko Kasama, Tadahiko Sugibayashi, 1995 .

Atomic Switch FPGA: Application for IoT Sensing Systems in Space

Yukio Mitsuyama, Hiroyuki Ochi, Hidetoshi Onodera, 2020 .

A non-volatile reconfigurable offloader for wireless sensor nodes

Yuichi Nakamura, Makoto Miyamura, Shogo Nakaya, 2012, CARN.

A 171k-LUT Nonvolatile FPGA using Cu Atom-Switch Technology in 28nm CMOS

Munehiro Tada, Naoki Banno, Makoto Miyamura, 2020, 2020 30th International Conference on Field-Programmable Logic and Applications (FPL).

Resistance ratio read (R/sup 3/) architecture for a burst operated 1.5V MRAM macro

Hiroaki Yoda, S. Tahara, Tadahiko Sugibayashi, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

Applications of Reconfigurable Processors as Embedded Automatons in the IoT Sensor Networks in Space

Yukio Mitsuyama, Hiroyuki Ochi, Kazutoshi Wakabayashi, 2019 .

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

Daisuke Suzuki, Shoji Ikeda, Tetsuo Endoh, 2015, IEEE Journal of Solid-State Circuits.

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications

Tetsuo Endoh, Takahiro Hanyu, Hiroaki Honjo, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications

Masanori Hashimoto, Yukio Mitsuyama, Hiroyuki Ochi, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A Non-volatile Reconfigurable Offloader for Wireless Sensor Nodes

Yuichi Nakamura, Makoto Miyamura, Shogo Nakaya, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture

Vincent Gripon, Tetsuo Endoh, Naoya Onizawa, 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Naoki Kasai, Ryusuke Nebashi, Noboru Sakimura, 2009, IEEE J. Solid State Circuits.

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme

Tetsuo Endoh, Takahiro Hanyu, Shoun Matsunaga, 2014, IEICE Electron. Express.

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, 2008, IEEE Journal of Solid-State Circuits.

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI

Takahiro Hanyu, Masanori Natsui, Noboru Sakimura, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

MRAM Applications Using Unlimited Write Endurance

Shuichi Tahara, Takeshi Honda, Noboru Sakimura, 2007, IEICE Trans. Electron..

Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS

Masato Motomura, Toshitsugu Sakamoto, Hiromitsu Hada, 2011, 2011 IEEE International Solid-State Circuits Conference.

Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory

Naoya Onizawa, Takahiro Hanyu, Ryusuke Nebashi, 2016, J. Multiple Valued Log. Soft Comput..

Non-complimentary rewriting and serial-data coding scheme for shared-sense-amplifier open-bit-line DRAMs

Tadahiko Sugibayashi, Satoshi Utsugi, M. Hanyu, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

Via-Switch FPGA: 65-nm CMOS Implementation and Evaluation

Toshitsugu Sakamoto, Munehiro Tada, Naoki Banno, 2021, IEEE Journal of Solid-State Circuits.

Material Stack Design With High Tolerance to Process-Induced Damage in Domain Wall Motion Device

Hiroaki Honjo, Kunihiko Ishihara, Keizo Kinoshita, 2014, IEEE Transactions on Magnetics.

Atom Switch with Improved Cycle Endurance using Field Enhancement for Nonvolatile SoC

Toshitsugu Sakamoto, Hiromitsu Hada, Yukihide Tsuji, 2018, 2018 IEEE International Memory Workshop (IMW).

Low-Power Crossbar Switch With Two-Varistor Selected Complementary Atom Switch (2V-1CAS; Via-Switch) for Nonvolatile FPGA

Masanori Hashimoto, Hiroyuki Ochi, Hidetoshi Onodera, 2019, IEEE Transactions on Electron Devices.

Etching Magnetic Tunnel Junction with Metal Etchers

Hiromitsu Hada, Keizo Kinoshita, Tadahiko Sugibayashi, 2010 .

27.4 A 90nm 12ns 32Mb 2T1MTJ MRAM

Naoki Kasai, S. Miura, Hiroaki Honjo, 2009 .

Three-terminal magnetic tunneling junction device with perpendicular anisotropy CoFeB sensing layer

Hiroaki Honjo, Kunihiko Ishihara, Keizo Kinoshita, 2014 .

A 30-ns 256-Mb DRAM with a multidivided array structure

Toshio Takeshima, K. Shibahara, Takaho Tanigawa, 1993 .

Magnetic tunneling junction with Fe/NiFeB free layer for magnetic logic circuits

Hiroaki Honjo, Hideo Ohno, Sadahiko Miura, 2012 .

Performance of shape-varying magnetic tunneling junction for high-speed magnetic random access memory cells

Hiroaki Honjo, Sadahiko Miura, Shunsuke Fukami, 2009 .