Josep L. Rosselló

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs

Jaume Segura, Josep L. Rosselló, C. de Benito, 2007 .

THERMAL-AWARE DESIGN RULES FOR NANOMETER ICs

Ali Keshavarzi, Jaume Segura, Josep L. Rosselló, 2005 .

Accurate modelling of leakage currents in nanometre CMOS technologies

Josep L. Rosselló, Jaume Segura, 2005 .

A variable threshold voltage inverter for CMOS programmable logic circuits

Jaume Segura, Josep L. Rosselló, H. Sigg, 1998 .

Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective

Jaume Verd, Josep L. Rosselló, S. Bota, 2016, Commun. Nonlinear Sci. Numer. Simul..

Standard-cell based temperature sensor for deep submicron CMOS technologies

Josep L. Rosselló, S. Bota, Jaume Segura, 2003 .

Exploiting Correlation in Stochastic Computing based Deep Neural Networks

Christiam F. Frasser, Pablo Linares-Serrano, V. Canals, 2021, 2021 XXXVI Conference on Design of Circuits and Integrated Systems (DCIS).

Hardware-Optimized Reservoir Computing System for Edge Intelligence Applications

Vincent Canals, Fabio Galan-Prado, Josep L. Rosselló, 2021 .

Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis

Jaume Segura, Josep L. Rosselló, 2002 .