Tai-Cheng Lee

发表

Nonlinear R-2R Transistor-Only DAC

Tai-Cheng Lee, Cheng-Hsiao Lin, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An %bit 2-V 2-mW 0.25-mm2 CMOS DAC

Hong-Sing Kao, Tai-Cheng Lee, Huei-Chi Wang, 2004 .

A 0.02-mm$^{2}$ 9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology

Tai-Cheng Lee, Yen-Chuan Huang, 2010, IEEE Journal of Solid-State Circuits.

2.4-GHz High-Efficiency Adaptive Power

Tai-Cheng Lee, Cheng-Jyun Li, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector

Po-Chun Huang, Tai-Cheng Lee, Wei-Sung Chang, 2014, IEEE Journal of Solid-State Circuits.

A 4-Channel Poly-Phase Filter for Cognitive Radio Systems

Tai-Cheng Lee, Hsien-Hsiang Chiu, Guan-Jun Chen, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

The Design and Analysis of Dual-Delay-Path

Zuow-Zun Chen, Tai-Cheng Lee, 2011 .

A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique

Tai-Cheng Lee, Chin-Yu Lin, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

An optimization technique for RF buffers with active inductors

Tai-Cheng Lee, Yen-Chuan Huang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 10-Gb/s equalizer with digital adaptation

Tai-Cheng Lee, Jui-Cheng Hsiao, Dai-En Jhou, 2017, 2017 International SoC Design Conference (ISOCC).

An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique

Yu-Hong Yang, Tai-Cheng Lee, Wei-Sung Chang, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation

Keng-Jan Hsiao, Tai-Cheng Lee, 2009, IEEE Journal of Solid-State Circuits.

A 40-GHz Distributed-Load Static Frequency Divider

Hua-Chin Lee, Keng-Jan Hsiao, Tai-Cheng Lee, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

A 5 GHz Fractional-$N$ ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

Tai-Cheng Lee, Wei-Sung Chang, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 10-bit binary-weighted DAC with digital background LMS calibration

Ding-Lan Shen, Tai-Cheng Lee, Yuan-Chun Lai, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit

Tai-Cheng Lee, Li-Hung Chiueh, 2014, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC).

An 8-bit 2-V 2-mW 0.25-mm/sup 2/ CMOS DAC

Hong-Sing Kao, Tai-Cheng Lee, Huei-Chi Wang, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling

Yu-Lun Hsieh, Tai-Cheng Lee, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier

Chorng-Kuang Wang, Hung-Chieh Tsai, Tai-Cheng Lee, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation

Keng-Jan Hsiao, Tai-Cheng Lee, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 6-b 1.3Gs/s A/D Converter with C-2C Switch-Capacitor Technique

Tai-Cheng Lee, Ying-Min Liao, 2006, 2006 International Symposium on VLSI Design, Automation and Test.

A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth

Tai-Cheng Lee, Wei-Sung Chang, Jia-An Jheng, 2014, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

A 10-bit 200-MS/s reconfigurable pipelined A/D converter

Chia-Chi Ho, Tai-Cheng Lee, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

A 10-bit piplined A/D converter with split calibration and opamp-sharing technique

Tai-Cheng Lee, Yen-Chuan Huang, Li-Han Hung, 2010, Proceedings of 2010 International Symposium on VLSI Design, Automation and Test.

An thermoelectric and RF multi-source energy harvesting system

Chia-Lun Chang, Tai-Cheng Lee, 2016, 2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG).

A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique

Tai-Cheng Lee, Yen-Chuan Huang, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

F2: FinFETs & FDSOI — A mixed signal circuit designer's perspective

Venkatesh Srinivasan, Tai-Cheng Lee, Stephane Le Tuai, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A 6-bit 500-Ms/s digital self-calibrated pipelined analog-to-digital converter

Yu-Hsun Chen, Tai-Cheng Lee, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

A 6-Bit 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers

Ding-Lan Shen, Tai-Cheng Lee, 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application

Tai-Cheng Lee, Yen-Chuan Huang, 2006 .

A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning

Keng-Jan Hsiao, Tai-Cheng Lee, 2007, 2007 IEEE Symposium on VLSI Circuits.

A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire

Behzad Razavi, Tai-Cheng Lee, 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

The Study of a Dual-Mode Ring Oscillator

Zuow-Zun Chen, Tai-Cheng Lee, 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

A stabilization technique for phase-locked frequency synthesizers

B. Razavi, Tai-Cheng Lee, B. Razavi, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers

Ding-Lan Shen, Tai-Cheng Lee, 2007, IEEE Journal of Solid-State Circuits.

CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90/spl deg/ delay network

Shen-Iuan Liu, Kun-Hsien Li, Chia-Hsin Wu, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link

Hao-Chung Kuo, Chao-Hsin Wu, Wood-Hi Cheng, 2017, 2017 Optical Fiber Communications Conference and Exhibition (OFC).

The Design and Analysis of Dual-Delay-Path Ring Oscillators

Zuow-Zun Chen, Tai-Cheng Lee, Tai-Cheng Lee, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 300- to 800-MHz de-skew clock generator for arbitrary delay

Tai-Cheng Lee, Yu-Cheng Hung, Kevin Fong, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

A clock and data recovery circuit with wide linear range frequency detector

Keng-Jan Hsiao, Tai-Cheng Lee, Ming-Hwa Lee, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

Tai-Cheng Lee, Chin-Yu Lin, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop

Tai-Cheng Lee, Hsiang-Chun Cheng, Yu-Hong Yang, 2020, 2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

IEEE Transactions on Circuits and Systems—II:Express Briefs publication information

Mohamad Sawan, Alyssa B. Apsel, Peng Li, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability

Chia-Lun Chang, Tai-Cheng Lee, 2014, 2014 International Symposium on Integrated Circuits (ISIC).

A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology

Tai-Cheng Lee, Chen-Kai Hsu, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Digitally assisted analog and RF circuits: Potentials and issues

Akira Matsuzawa, Asad A. Abidi, Boris Murmann, 2008 .

A 10-bit 400-MS/s 36-mW interleaved ADC

Tai-Cheng Lee, Chin-Yu Lin, Yen-Chuan Huang, 2011, 2011 IEEE International Symposium on Radio-Frequency Integration Technology.

A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique

Tai-Cheng Lee, Chin-Yu Lin, Yen-Hsin Wei, 2018, IEEE Journal of Solid-State Circuits.

27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration

Tai-Cheng Lee, Chin-Yu Lin, Yen-Hsin Wei, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

An all-digital de-skew clock generator for arbitrary wide range delay

Zuow-Zun Chen, Tai-Cheng Lee, Yu-Cheng Hung, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

A 84.7-DR wide BW incremental ADC using CT structure

Tai-Cheng Lee, Ting-Yang Wang, 2015, VLSI Design, Automation and Test(VLSI-DAT).

A mixed-signal GFSK demodulator for Bluetooth

Tai-Cheng Lee, Chin-Chi Chen, 2006, IEEE Trans. Circuits Syst. II Express Briefs.

A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration

Tai-Cheng Lee, Chin-Yu Lin, Yen-Hsin Wei, 2016, 2016 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

A technique for in-band phase noise reduction in fractional-N frequency synthesizers

Tai-Cheng Lee, Chun-Ping Wang, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire

Behzad Razavi, Tai-Cheng Lee, 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire

Behzad Razavi, Tai-Cheng Lee, 2001 .

21.2 A 2.3GHz fractional-N dividerless phase-locked loop with −112dBc/Hz in-band phase noise

Po-Chun Huang, Tai-Cheng Lee, Wei-Sung Chang, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

High-precision frequency synthesizers for UWB applications

Keng-Jan Hsiao, Tai-Cheng Lee, Yen-Chuang Huang, 2005, Conference, Emerging Information Technology 2005..

A Multiphase Compensation Method with Dynamic Element Matching Technique in Σ-∆ Fractional-N Frequency Synthesizers

Zuow-Zun Chen, Tai-Cheng Lee, 2008 .

25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique

Tai-Cheng Lee, Hsiu-Hsien Ting, Tai-Cheng Lee, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).

A Miller divider based clock generator for MBOA-UWB application

Tai-Cheng Lee, Yen-Chuang Huang, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator

Chien-Heng Wong, Tai-Cheng Lee, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications

Chia-Lun Chang, Tai-Cheng Lee, 2016, J. Circuits Syst. Comput..

Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies

Tai-Cheng Lee, Chin-Yu Lin, Yen-Chuan Huang, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

A 14-Gb/s 4-PAM Adaptive Analog Equalizer for 40-inch Backplane Interconnections

Qui-Ting Chen, Tai-Cheng Lee, Yen-Chuan Huang, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator

Tai-Cheng Lee, Chin-Yu Lin, Yu-Hsuan Kang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

A 4-PAM adaptive analog equalizer for backplane interconnections

Qui-Ting Chen, Tai-Cheng Lee, Yen-Chuan Huang, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

An offset phase-locked loop spread spectrum clock generator for SATA III

Tai-Cheng Lee, Chin-Yu Lin, Chun-Yu Chiang, 2010, IEEE Custom Integrated Circuits Conference 2010.

A Split-Based Digital Background Calibration Technique in Pipelined ADCs

Tai-Cheng Lee, Li-Han Hung, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning

Keng-Jan Hsiao, Tai-Cheng Lee, 2008, IEEE Journal of Solid-State Circuits.

A DLL-based frequency multiplier for MBOA-UWB system

Keng-Jan Hsiao, Tai-Cheng Lee, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 6-bit pipelined analog-to-digital converter with current-switching open-loop residue amplification

Tai-Cheng Lee, Fen-Chiu Hsieh, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

Ultra-low-power one-pin crystal oscillator with self-charged technique

Tai-Cheng Lee, Shang-Chi Wu, 2016 .

Jitter error cancellation technique in digital domain for ADC

Tai-Cheng Lee, Chin-Yu Lin, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

An 833-MHz 132-phase multiphase clock generator with self-calibration circuits

Shih-Chun Lin, Tai-Cheng Lee, 2008, 2008 IEEE Asian Solid-State Circuits Conference.

Session 15 overview: Oversampling data converters

Venkatesh Srinivasan, Tai-Cheng Lee, 2016, ISSCC.

A 2×25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology

Tai-Cheng Lee, Wei-Sung Chang, Bo-Jing Lin, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique

Tai-Cheng Lee, Yen-Chuan Huang, 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Delay-Line-Based GFSK Demodulator for Low-IF Receivers

Hong-Sing Kao, Tai-Cheng Lee, Ming-Jen Yang, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 200-MS/s Phase-Detector-Based Comparator With 400-$\mu\text{V}_{\mathrm{rms}}$ Noise

Chien-Heng Wong, Tai-Cheng Lee, Chin-Yu Lin, 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Spur Suppression Technique for Phase-Locked Frequency Synthesizers

Wei-Liang Lee, Tai-Cheng Lee, 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

A linear-approximation technique for digitally-calibrated pipelined A/D converters

Ding-Lan Shen, Tai-Cheng Lee, 2005, 2005 IEEE International Symposium on Circuits and Systems.

The design and analysis of a DLL-based frequency synthesizer for UWB application

Keng-Jan Hsiao, Tai-Cheng Lee, 2006 .

SSCS-Taipei Chapter Holds Integrated Circuit Design Workshop on Ultra-Low-Voltage Design in Advanced CMOS Technology [Conference Reports]

Tzi-Dar Chiueh, Tsung-Te Liu, Tai-Cheng Lee, 2016 .