Xuqiang Zheng

发表

A 5+ 1-lane 3–10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology

Kunzhi Yu, Zhihua Wang, Ke Huang, 2014 .

2 GHz sub-harmonically injection-locked PLL with mixer-based injection timing control in 0.18 µm CMOS technology

Zhihua Wang, Ke Huang, Ziqiang Wang, 2014 .

A 75mW 50Gbps SerDes transmitter with automatic serializing time window search in 65nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

A 10Gb/s source-synchronous transmitter in 65nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2014, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits.

A 50–112-Gb/s PAM-4 Transmitter With a Fractional-Spaced FFE in 65-nm CMOS

Xuqiang Zheng, Jin Wu, Feng Zhao, 2020, IEEE Journal of Solid-State Circuits.

A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology

Zhihua Wang, Ziqiang Wang, Xuqiang Zheng, 2019 .

A 40 Gb/s SerDes Transceiver Chip with Controller and PHY in a 65 nm CMOS Technology

Hao Ding, Ziqiang Wang, Xuqiang Zheng, 2019 .

A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

A 10Gb/s analog equalizer in 0.18um CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2013, 2013 IEEE 10th International Conference on ASIC.

A 40Gb/s 27mW 3-tap closed-loop decision feedback equalizer in 65nm CMOS

Zhihua Wang, Ziqiang Wang, Ke Huang, 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolators

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset With 40 dB of Equalization in 65 nm CMOS Technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 40-Gb/s Quarter-Rate SerDes Transmitter and Receiver Chipset in 65-nm CMOS

Hanjun Jiang, Feng Zhao, Chun Zhang, 2017, IEEE Journal of Solid-State Circuits.

Incoherent photonic digital-to-analogue converter based on broadband optical source

Xuqiang Zheng, Hongyu Zhang, Xiaobao Yu, 2007 .

A 6.4 Gb/s data lane design for forwarded clock receiver in 65nm CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology

Zhihua Wang, Chun Zhang, Woogeun Rhee, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology

Ziqiang Wang, Xuqiang Zheng, Chun Zhang, 2014 .

An Adaptive Floating-tap Decision Feedback Equalizer for a 2.5 to 10 Gbps Receiver

Xuqiang Zheng, Chen Cai, Jianzhong Zhao, 2019, 2019 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA).

2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

Zhihua Wang, Ke Huang, Ziqiang Wang, 2014 .

A 5-50 Gb/s quarter rate transmitter with a 4-tap multiple-MUX based FFE in 65 nm CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A Robust Visual System for Small Target Motion Detection Against Cluttered Moving Backgrounds

Xuqiang Zheng, Jigen Peng, Shigang Yue, 2019, IEEE Transactions on Neural Networks and Learning Systems.

Design of 80-Gb/s PAM4 wireline receiver in 65-nm CMOS technology

Zhihua Wang, Hanjun Jiang, Ziqiang Wang, 2017, 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).

A 50Gb/s low power PAM4 SerDes transmitter with 4-tap FFE and high linearity output voltage in 65nm CMOS technology

Ziqiang Wang, Xuqiang Zheng, Fule Li, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A battery-less, 255 nA quiescent current temperature sensor with voltage regulator fully powered by harvesting ambient vibrational energy

Peng Wang, Philip X.-L. Feng, Xuqiang Zheng, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

A 10Gb/s speculative decision feedback equalizer with a novel implementation of adaption in 65nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2014, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits.

A 40Gb/s 39mW 3-tap adaptive closed-loop decision feedback equalizer in 65nm CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2015, 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS).

A power scalable 2-10 Gb/s PI-based clock data recovery for multilane applications

Zhihua Wang, Hanjun Jiang, Ziqiang Wang, 2018, Microelectron. J..

A 28-Gb/s transmitter with 3-tap FFE and T-coil enhanced terminal in 65-nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2016, 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS).

A 14-bit 250 MS/s IF Sampling Pipelined ADC in 180 nm CMOS Process

Xuqiang Zheng, Shigang Yue, Feng Zhao, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 µm SiGe-BiCMOS

Lei Zhou, Dong Wang, Xinyu Liu, 2019, IEICE Electron. Express.

A novel clock and data recovery scheme for 10Gbps source synchronous receiver in 65nm CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2012, 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS).

10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology

Zhihua Wang, Ziqiang Wang, Xuqiang Zheng, 2015 .

A 6.4 Gb/s source synchronous receiver core with variable offset equalizer in 65nm CMOS

Ziqiang Wang, Xuqiang Zheng, Kunzhi Yu, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

A current-to-voltage integrator using area-efficient correlated double sampling technique

Xuan Wang, Chun Zhang, Xuqiang Zheng, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2015, 2015 IEEE Custom Integrated Circuits Conference (CICC).

Design of high-speed SerDes transceiver for chip-to-chip communications in CMOS process

Xuqiang Zheng, Xuqiang Zheng, 2018 .

A 80 mW 40 Gb/s Transmitter With Automatic Serializing Time Window Search and 2-tap Pre-Emphasis in 65 nm CMOS Technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 10Gbps CDR based on phase interpolator for source synchronous receiver in 65nm CMOS

Zhihua Wang, Chun Zhang, Ke Huang, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A 15Gb/s wireline repeater in 65nm CMOS technology

Zhihua Wang, Ziqiang Wang, Xuqiang Zheng, 2015, 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).

A 76 mW 40-Gb/s SerDes transmitter with 64:1 MUX In 65-nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2016, 2016 6th International Conference on Electronics Information and Emergency Communication (ICEIEC).

A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology

Zhihua Wang, Ziqiang Wang, Ke Huang, 2013, 2013 IEEE 10th International Conference on ASIC.

A 112-Gb/s PAM-4 Transmitter With a 2-Tap Fractional-Spaced FFE in 65-nm CMOS

Jin Wu, Xuqiang Zheng, Danyu Wu, 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

A 4–40 Gb/s PAM4 transmitter with output linearity optimization in 65 nm CMOS

Zhihua Wang, Hanjun Jiang, Ziqiang Wang, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

A 48mW 15-to-28Gb/s source-synchronous receiver with adaptive DFE using hybrid alternate clock scheme and baud-rate CDR in 65nm CMOS

Ziqiang Wang, Chun Zhang, Peng Wang, 2015, ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC).

Research on high speed mixed-signal SoC verification based on NanoSim-VCS with a 4.8Gb/s SerDes transmitter

Ziqiang Wang, Xiangmin Zhang, Xuqiang Zheng, 2012, 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology.

Co-design of 40Gb/s equalizers for wireline transceiver in 65nm CMOS technology

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2014, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits.

A Low-Distortion 20 GS/s Four-Channel Time-Interleaved Sample-and-Hold Amplifier in 0.18 μm SiGe BiCMOS

Jin Wu, Xuqiang Zheng, Xinyu Liu, 2019, Electronics.

A 40Gbps quarter rate CDR using CMOS-style signal alignment strategy in 65nm CMOS

Zhihua Wang, Ziqiang Wang, Chun Zhang, 2014, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits.

A multiphase clock generation based on DLL for source synchronous receiver in 65nm CMOS technology

Zhihua Wang, Ke Huang, Ziqiang Wang, 2013, International Conference on Graphic and Image Processing.

A 10–60 Gb/s wireline transmitter with a 4-tap multiple-MUX based FFE

Zhihua Wang, Hanjun Jiang, Ziqiang Wang, 2017, 2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC).

A 4.8-mW/Gb/s 9.6-Gb/s 5 $+$ 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

Ziqiang Wang, Chun Zhang, Woogeun Rhee, 2014, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 10 GHz 56 fsrms-integrated-jitter and −247 dB FOM ring-VCO based injection-locked clock multiplier with a continuous frequency-tracking loop in 65 nm CMOS

Zhihua Wang, Hanjun Jiang, Ziqiang Wang, 2017, 2017 IEEE Custom Integrated Circuits Conference (CICC).

Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators

Jin Wu, Xuqiang Zheng, Chun Zhang, 2020, IEEE Journal of Solid-State Circuits.

A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration

Xuqiang Zheng, Xinyu Liu, Jin Wu, 2020 .

A 40–80 Gb/s PAM4 wireline transmitter in 65nm CMOS technology

Ziqiang Wang, Xuqiang Zheng, Chun Zhang, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

A 25Gb/s adaptive decision feedback equalizer for 100G Ethernet in 65NM CMOS technology

Ziqiang Wang, Jinxing Guo, Xuqiang Zheng, 2014, 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

Jin Wu, Xuqiang Zheng, Lei Zhou, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

A Real-Time Output 50-GS/s 8-bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency

Jin Wu, Xuqiang Zheng, Lei Zhou, 2021, ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC).

A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Jin Wu, Xuqiang Zheng, Lei Zhou, 2021, Electronics.