Chun Zhang

发表

A 5+ 1-lane 3–10 Gbps 3.5 mW/Gb/s source synchronous receiver in 65 nm CMOS technology

Kunzhi Yu, Zhihua Wang, Ke Huang, 2014 .

2 GHz sub-harmonically injection-locked PLL with mixer-based injection timing control in 0.18 µm CMOS technology

Zhihua Wang, Ke Huang, Ziqiang Wang, 2014 .

A 20 GHz subharmonic injection-locked clock multiplier with mixer-based injection timing control in 65 nm CMOS technology

Zhihua Wang, Ziqiang Wang, Xuqiang Zheng, 2019 .

A 9-Gb/s quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology

Ziqiang Wang, Xuqiang Zheng, Chun Zhang, 2014 .

2-tap pre-emphasis SST transmitter with skin effect loss equalisation in 65 nm CMOS technology

Zhihua Wang, Ke Huang, Ziqiang Wang, 2014 .

Modeling of a Schottky diode in CMOS process with a flexible “open-through” On-Chip De-embedding Method

Yongming Li, Zhihua Wang, Chun Zhang, 2011 .

Fast trajectory tracking of electromagnetic satellite formation with actuator saturation

Chun Zhang, Hang Yin, Xianlin Huang, 2016 .

An LMI-based decoupling control for electromagnetic formation flight

Chun Zhang, Hang Yin, Xianlin Huang, 2015 .

10 Gbit/s serial link receiver with speculative decision feedback equaliser using mixed-signal adaption in 65 nm CMOS technology

Zhihua Wang, Ziqiang Wang, Xuqiang Zheng, 2015 .

Low-power circuits for the wireless ligament balance measurement system in TKA

Zhihua Wang, Hong Chen, Hanjun Jiang, 2012 .

An IP-oriented 11-bit 160 MS/s 2-channel current-steering DAC

Chun Zhang, Ning Xu, Fule Li, 2014 .

Design of UHF RFID Tag with On-Chip Antenna

Yongming Li, Ziqiang Wang, Chun Zhang, 2012 .

A multiphase clock generation based on DLL for source synchronous receiver in 65nm CMOS technology

Zhihua Wang, Ke Huang, Ziqiang Wang, 2013, International Conference on Graphic and Image Processing.