A. Naem

Drain engineering of hot-carrier-resistant MOSFETs using concave silicon surfaces for deep submicron VLSI technology

P. Ratnam, A. Naem, 1990 .

Integrated passives for a DECT VCO

Eric Beyne, Kristof Vaesen, P. Pieters, 2000 .

Closed form inductance calculation for integrated spiral inductor compact modeling

S. Decoutere, B. Nauwelaers, S. Jenei, 2000, 2000 Topical Meetings on Silicon Monolithic Integrated Circuits in RF Systems. Digest of Papers (Cat. No.00EX397).

Influence of gate length on ESD-performance for deep sub micron CMOS technology

Guido Groeseneken, Karlheinz Bock, A. Naem, 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

Investigation of intrinsic transistor performance of advanced CMOS devices with 2.5 nm NO gate oxides

L. Deferm, P. Jansen, D. Kerr, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Influence of gate length on ESD-performance for deep sub micron CMOS technology

Guido Groeseneken, B. Keppens, A. Naem, 1999 .

Temperature acceleration of oxide breakdown and its impact on ultra-thin gate oxide reliability

T. Nigam, R. Degraeve, B. Kaczer, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime

Stefan Kubicek, K. De Meyer, Eric M. Vogel, 2000 .