Somayeh Timarchi

发表

Arithmetic Circuits of Redundant SUT-RNS

Keivan Navi, Somayeh Timarchi, 2009, IEEE Transactions on Instrumentation and Measurement.

Fast architecture for decimal digit multiplication

Hadi Tabatabaee Malazi, Mahmood Fazlali, Somayeh Timarchi, 2015, Microprocess. Microsystems.

Area-Time-Power Efficient Maximally Redundant Signed-Digit Modulo 2n − 1 Adder and Multiplier

Somayeh Timarchi, Negar Akbarzadeh, S. Timarchi, 2018, Circuits Syst. Signal Process..

Improved Modulo 2n +1 Adder Design

Keivan Navi, Somayeh Timarchi, K. Navi, 2008 .

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles

Somayeh Timarchi, Hossein Mahdavi, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Efficient 1-out-of-3 Binary Signed-Digit multiplier for the moduli set {2n-1, 2n, 2n+1}

Somayeh Timarchi, Maryam Saremi, 2013, The 17th CSI International Symposium on Computer Architecture & Digital Systems (CADS 2013).

Optimized Parity-Based Error Detection and Correction Methods for Residue Number System

Somayeh Timarchi, Hossein Mahdavi, Adib Armand, 2019, J. Circuits Syst. Comput..

Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2n - 1, 2n, 2n + 1}

Mahmood Fazlali, Somayeh Timarchi, 2012, IET Comput. Digit. Tech..

Efficient Reverse Converter Designs for the New 4-Moduli Sets $\{2^{n} -1, 2^{n}, 2^{n} +1, 2^{2n + 1}-1\}$ and $\{2^{n} -1, 2^{n} +1, 2^{2n}, 2^{2n} +1\}$ Based on New CRTs

Omid Kavehei, Keivan Navi, Somayeh Timarchi, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Modulo 2n+1 Multiply and MAC Units Specified for DSPs

Somayeh Timarchi, Negar Akbarzadeh, 2018 .

An efficient power-area-delay modulo 2n−1 multiplier

Mahmood Fazlali, Somayeh Timarchi, 2010, 2010 15th CSI International Symposium on Computer Architecture and Digital Systems.

Novel algorithm and architectures for high-speed low-power ConText-based steganography

Somayeh Timarchi, Masoud Abbasi Alaei, Hossein Koushkbaghi, 2017, 2017 19th International Symposium on Computer Architecture and Digital Systems (CADS).

Maximally redundant high-radix Signed-Digit Residue Number System

Somayeh Timarchi, Negar Akbarzadeh, Amir Abbas Hamidi, 2015, 2015 18th CSI International Symposium on Computer Architecture and Digital Systems (CADS).

Area–Time–Power Efficient FFT Architectures Based on Binary-Signed-Digit CORDIC

Somayeh Timarchi, Hossein Mahdavi, 2019, IEEE Transactions on Circuits and Systems I: Regular Papers.

Ultra-low voltage standard cell libraries: Design strategies and a case study

Massimo Alioto, Somayeh Timarchi, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

A novel low-power full-adder cell for low voltage

Omid Kavehei, Keivan Navi, Somayeh Timarchi, 2009, Integr..

A unified addition structure for moduli set {2n−1, 2n, 2n+1} based on a novel RNS representation

Mahmood Fazlali, Somayeh Timarchi, Sorin Cotofana, 2010, 2010 IEEE International Conference on Computer Design.

Evaluation of Some Exponential Random Number Generators Implemented by FPGA

Somayeh Timarchi, Seyed Ghassem Miremadi, Alireza Ejlali, 2005, Parallel and Distributed Computing and Networks.

Efficient error detection and correction method for 1-out-of-3 binary signed digit adders

Somayeh Timarchi, Adib Armand, S. Timarchi, 2019, International Journal of Electronics.

A new algorithm for determining all possible symmetric hybrid redundant numbers

Keivan Navi, Somayeh Timarchi, 2009, IEICE Electron. Express.

Efficient modulo 2n +1 multiplier

Somayeh Timarchi, Masoud Abbasi Alaie, 2016, Int. J. Comput. Aided Eng. Technol..

Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix

Somayeh Timarchi, Hossein Mahdavi, Ahmad Shabani, 2019, Microelectron. J..

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

Somayeh Timarchi, Mohammad Hossein Moaiyeri, Mohammad Eshghi, 2016, Circuits Syst. Signal Process..

Maximally Redundant High-Radix Signed-Digit Adder: New Algorithm and Implementation

Omid Kavehei, Keivan Navi, Somayeh Timarchi, 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

High-speed energy-efficient 5:2 compressor

Amir Najafi, Somayeh Timarchi, Ardalan Najafi, 2014, 2014 37th International Convention on Information and Communication Technology, Electronics and Microelectronics (MIPRO).

Low-power DCT-based compressor for wireless capsule endoscopy

Somayeh Timarchi, Ahmad Shabani, 2017, Signal Process. Image Commun..

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

Somayeh Timarchi, Hamed Naseri, S. Timarchi, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low power design of binary signed digit residue number system adder

Somayeh Timarchi, Adib Armand, 2016, 2016 24th Iranian Conference on Electrical Engineering (ICEE).

High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding

Mahmood Fazlali, Somayeh Timarchi, Georgi Gaydadjiev, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Area and Power-Efficient Variable-Sized DCT Architecture for HEVC Using Muxed-MCM Problem

Somayeh Timarchi, Ahmad Shabani, Bahareh Khabbazan, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low Power Modulo 2n+1 Adder Based on Carry Save Diminished-One Number System

Omid Kavehei, Keivan Navi, Somayeh Timarchi, 2008 .

Radix-4 implementation of redundant interleaved modular multiplication on FPGA

Mohammad Eshghi, Somayeh Timarchi, Loghman Rahimzadeh, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).