Jun Jin Kong

发表

Kyeongcheol Yang, Jaeyong Son, Jun Jin Kong, 2018, Journal of Communications and Networks.

Low-latency architectures for high-throughput rate Viterbi decoders

Keshab K. Parhi, Jun Jin Kong, 2004, IEEE Trans. Very Large Scale Integr. Syst..

A modified two-step SOVA-based turbo decoder for low power and high performance

Jun Rim Choi, Dae Won Kim, Ki-Won Lee, 1999, Proceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030).

Verify level control criteria for multi-level cell flash memories and their applications

B. V. K. Vijaya Kumar, Xin Li, Yongjune Kim, 2012, EURASIP J. Adv. Signal Process..

Modulation coding for flash memories

B. V. K. Vijaya Kumar, Jaejin Lee, Yongjune Kim, 2013, 2013 International Conference on Computing, Networking and Communications (ICNC).

Error control coding and signal processing for flash memories

Beomkyu Shin, Jun Jin Kong, Changkyu Seol, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A fast serial Viterbi decoder ASIC for CDMA cellular base station

Youngky Kim, Jun Jin Kong, Min-Goo Kim, 1996, Proceedings of Digital Processing Applications (TENCON '96).

K-nested layered look-ahead method and architectures for high throughput Viterbi decoder

Keshab K. Parhi, Jun Jin Kong, 2003, 2003 IEEE Workshop on Signal Processing Systems (IEEE Cat. No.03TH8682).

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme

Nam Sung Kim, Jae Hoon Lee, Seouk-Kyu Choi, 2021, IEEE Journal of Solid-State Circuits.

High-speed add-compare-select units using locally self-resetting CMOS

Keshab K. Parhi, Gerald E. Sobelman, Jun Jin Kong, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

Low-Latency Architectures for High-Throughput

Keshab K. Parhi, Jun Jin Kong, K. Parhi, 2004 .

A modified two-step SOVA-based turbo decoder with a fixed scaling factor

Jun Rim Choi, Jun Jin Kong, Taek Won Kwon, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Interleaved cyclic redundancy check (CRC) code

Keshab K. Parhi, Jun Jin Kong, K. Parhi, 2003, The Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003.

Apparatus and method for generation and distribution of encoded symbols in a CDMA communications system

Jong-Seon No, Chang-soo Park, Jun Jin Kong, 1999 .

A post-processing algorithm for reducing strong error effects in NAND flash memory

Gyuyeol Kong, Dongmin Shin, Beomkyu Shin, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

Interleaved Convolutional Code and Its Viterbi Decoder Architecture

Keshab K. Parhi, Jun Jin Kong, K. Parhi, 2003, EURASIP J. Adv. Signal Process..

Channel encoding method and apparatus and data transmission device in a CDMA communication system

Chang-soo Park, Jun Jin Kong, Jae Kim, 1999 .

Viterbi detector architecture for high speed optical storage

Jun Jin Kong, Yong Hwan Kim, Sung Han Choi, 1997, TENCON '97 Brisbane - Australia. Proceedings of IEEE TENCON '97. IEEE Region 10 Annual Conference. Speech and Image Technologies for Computing and Telecommunications (Cat. No.97CH36162).

Viterbi decoder architecture for interleaved convolutional code

K.K. Parhi, Jun Jin Kong, 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme

Nam Sung Kim, Seouk-Kyu Choi, Jung-Bae Lee, 2020, 2020 IEEE International Solid- State Circuits Conference - (ISSCC).