C. Ito

Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applications

R.W. Dutton, C. Ito, K. Banerjee, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

Design Methodology and Protection Strategy for ESD-CDM Robust Digital System Design in 90-nm and 130-nm Technologies

R.W. Dutton, S. Mitra, C. Ito, 2009, IEEE Transactions on Electron Devices.

A new mechanism for core device failure during CDM ESD events

C. Ito, W. Loh, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

Gate oxide reliability characterization in the 100ps regime with ultra-fast transmission line pulsing system

R.W. Dutton, C. Ito, Tze Wee Chen, 2007, 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD).

Analysis and design of distributed ESD protection circuits for high-speed mixed-signal and RF ICs

Kaustav Banerjee, Robert W. Dutton, C. Ito, 2002 .

A frequency-domain VFTLP pulse characterization methodology and its application to CDM ESD modeling

C. Ito, Tze Wee Chen, W. Loh, 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.