K. Banerjee

Analysis and optimization of distributed ESD protection circuits for high-speed mixed-signal and RF applications

R.W. Dutton, C. Ito, K. Banerjee, 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

Accurate analysis of on-chip inductance effects and implications for optimal repeater insertion and technology scaling

K. Banerjee, A. Mehrotra, K. Banerjee, 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

3-D ICs: Motivation, performance analysis, and technology

P. Kapur, K.C. Saraswat, K. Banerjee, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Power dissipation issues in interconnect performance optimization for sub-180 nm designs

K. Banerjee, A. Mehrotra, 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

A Zero Phase-lag Homodyne Demodulation Technique for Synchronous Measurement Applications and its Fpga Implementation

K. Banerjee, B. Dam, D. Patranabis, 2005, J. Circuits Syst. Comput..

Total Radiated Power Measurement Results of Multimedia products in Reverberation Chamber; Unintentional radiators

K. Banerjee, 2009 .