Y. Taguchi

Development of less expensive process technologies for three-dimensional chip stacking with through-vias

Kazumasa Tanida, Mitsuo Umemoto, Toshihiro Yonezawa, 2004 .

Report on the Seventh U.S.–Japan Joint Seminar on Nanoscale Transport Phenomena—Science and Engineering

A. McGaughey, K. Pipe, J. Lukes, 2008 .

Development of silicon module with TSVs and global wiring (L/S=0.8/0.8µm)

K. Murayama, Masahiro Sunohara, M. Sunohara, 2009, 2009 59th Electronic Components and Technology Conference.

High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking II. Reduced Electrodeposition Process Time

K. Kondo, D. Barkey, D. Mikami, 2005 .

Copper Via Filling Electrodeposition of High Aspect Ratio Through Chip Electrodes Used for the Three Dimensional Packaging

Seung Jin Oh, M. Tomisaka, Hitoshi Yonemura, 2003 .

Process integration of 3D chip stack with vertical interconnection

Y. Yamaji, M. Tomisaka, H. Yonemura, 2004, 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546).