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Process-Induced Gate Oxide Damage Issues in Advanced Plasma Chemical Vapor Deposition Processes

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BEOL Cu CMP Process Evaluation for Advanced Technology Nodes

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Vertical-Transport Nanosheet Technology for CMOS Scaling beyond Lateral-Transport Devices

A. Young, H. Jagannathan, J. Demarest, 2021, 2021 IEEE International Electron Devices Meeting (IEDM).

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

B. Lherron, D. Chanemougame, P. Oldiges, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.

Hardware Based Performance Assessment of Vertical-Transport Nanosheet Technology

H. Jagannathan, J. Demarest, M. Sankarapandian, 2022, International Electron Devices Meeting.

Conference of Microelectronic Research 1990

Joseph Johnson, William Roberts, Brian Izzio, 1990 .