H. R. Bhagyalakshmi

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A Case Study: Improved Learning through Course Assessment

D. Ajay Kumar, H. R. Bhagyalakshmi, D. Seshachalam, 2015 .

Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit pdf

Rakshith Saligram, H. R. Bhagyalakshmi, M. K. Venkatesha, 2013, VLSIC 2013.

Student Performance using Blooms Cognition Levels: A Case Study

H. R. Bhagyalakshmi, D. Seshachalam, 2015 .

Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates

Rakshith Saligram, H. R. Bhagyalakshmi, M. K. Venkatesha, 2013 .

Toffoli Cascade Synthesis of an Optimized Two-Bit Comparator

H. R. Bhagyalakshmi, M. K. Venkatesha, 2014 .

Optimized reversible BCD adder using new reversible logic gates pdf

H. R. Bhagyalakshmi, M. K. Venkatesha, 2010, ArXiv.

Program Outcome Attainment Through Course Outcomes: A Comprehensive Approach

H. R. Bhagyalakshmi, D. Seshachalam, S. Lalitha, 2015 .

Design of Sequential Circuit Elements Using Reversible Logic Gates - TI Journals

H. R. Bhagyalakshmi, M. K. Venkatesha, 2012 .

Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving

H. R. Bhagyalakshmi, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, 2013 .

An Optimized Multiplier Using Reversible Logic Gates

H. R. Bhagyalakshmi, 2012 .

Optimized Reversible carry select BCD a dders using Reversible logic gates

H. R. Bhagyalakshmi, M. Venkatesha, 2012 .

Optimized design of BCD adder and Carry skip BCD adder using reversible logic gates

H. R. Bhagyalakshmi, M. Venkatesha, 2011 .

AN IMPROVED DESIGN OF A MULTIPLIER USING REVERSIBLE LOGIC GATES

H. R. Bhagyalakshmi, H. R. BHAGYALAKSHMI, 2010 .

Low Power FPGA Architecture

H. R. Bhagyalakshmi, Abhijeet Khandale, H. Bhagyalakshmi, 2015 .