John D. Leidel

发表

HMC-Sim-2.0: A Simulation Platform for Exploring Custom Memory Cube Operations

Yong Chen, John D. Leidel, Yong Chen, 2016, 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

OpenSoC system architect: An open toolkit for building soft-cores on FPGAs

John Shalf, Farzad Fatollahi-Fard, David Donofrio, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Toward a Microarchitecture for Efficient Execution of Irregular Applications

Yong Chen, Xi Wang, John D. Leidel, 2020, ACM Trans. Parallel Comput..

GoblinCore-64: A RISC-V Based Architecture for Data Intensive Computing

Yong Chen, Xi Wang, John D. Leidel, 2018, 2018 IEEE High Performance extreme Computing Conference (HPEC).

PAC: Paged Adaptive Coalescer for 3D-Stacked Memory

Yong Chen, Xi Wang, John D. Leidel, 2020, HPDC.

Pressure-Driven Hardware Managed Thread Concurrency for Irregular Applications

Yong Chen, Xi Wang, John D. Leidel, 2017, IA3@SC.

Exploring Tag-Bit Memory Operations in Hybrid Memory Cubes

Yong Chen, John D. Leidel, 2016, MEMSYS.

HMC-Sim-2.0: A co-design infrastructure for exploring custom memory cube operations

Yong Chen, John D. Leidel, 2017, Parallel Comput..

Collective Communication for the RISC-V xBGAS ISA Extension

John D. Leidel, Yong Chen, Xi Wang, 2019, ICPP Workshops.

PIMS: a lightweight processing-in-memory accelerator for stencil computations

Jie Li, Antonino Tumeo, John D. Leidel, 2019, MEMSYS.

Memory Coalescing for Hybrid Memory Cube

John D. Leidel, Yong Chen, Xi Wang, 2018, ICPP.

Concurrent Dynamic Memory Coalescing on GoblinCore-64 Architecture

Yong Chen, Xi Wang, John D. Leidel, 2016, MEMSYS.

GoblinCore64: Architectural Specication Technical Report 2015-001

Xi Wang, John D. Leidel, 2015 .

POSTER: Memory Hotspot Optimization for Data-Intensive Applications

Jie Li, Antonino Tumeo, John D. Leidel, 2019, 2019 28th International Conference on Parallel Architectures and Compilation Techniques (PACT).

HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices

Yong Chen, John D. Leidel, Yong Chen, 2014, 2014 IEEE International Parallel & Distributed Processing Symposium Workshops.

Toward a Scalable Heterogeneous Runtime System for the Convey MX Architecture

John D. Leidel, Geoffrey Rogers, Joe Bolding, 2013, 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum.

Bit Contiguous Memory Allocation for Processing In Memory

John D. Leidel, 2017, MCHPC@SC.

xBGAS: Toward a RISC-V ISA Extension for Global, Scalable Shared Memory

Farzad Fatollahi-Fard, David Donofrio, John D. Leidel, 2018, MCHPC@SC.

Communication Avoiding Power Scaling

Yong Chen, John D. Leidel, 2015, 2015 44th International Conference on Parallel Processing Workshops.

GoblinCore-64: A scalable, open architecture for data intensive high performance computing

John D. Leidel, 2017 .

CHOMP: A Framework and Instruction Set for Latency Tolerant, Massively Multithreaded Processors

John D. Leidel, Tony Brewer, Kevin Wadleigh, 2012, 2012 SC Companion: High Performance Computing, Networking Storage and Analysis.

Toward a graph-based dependence analysis framework for high level design verification

John D. Leidel, Frank Conlon, Frank Conlon, 2019, CF.

OpenMP Memkind: An Extension for Heterogeneous Physical Memories

Yong Chen, Xi Wang, John D. Leidel, 2017, 2017 46th International Conference on Parallel Processing Workshops (ICPPW).

MAC: Memory Access Coalescer for 3D-Stacked Memory

Antonino Tumeo, John D. Leidel, Jie Li, 2019, ICPP.

Remote Atomic Extension (RAE) for Scalable High Performance Computing

Yong Chen, Xi Wang, John D. Leidel, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

StoneCutter: a very high level instruction set design language

David Donofrio, John D. Leidel, Frank Conlon, 2020, CF.

Stake: a coupled simulation environment for RISC-V memory experiments

John D. Leidel, 2018, MEMSYS '18.

HMC-Sim: A Simulation Framework for Hybrid Memory Cube Devices

Yong Chen, John D. Leidel, 2014, IPDPS Workshops.

Toward HDL Extensions for Rapid AI/ML Accelerator Generation

David Donofrio, John D. Leidel, Ryan Kabrick, 2021, 2021 IEEE High Performance Extreme Computing Conference (HPEC).

Toward an Automated Hardware Pipelining LLVM Pass Infrastructure

David Donofrio, John D. Leidel, Ryan Kabrick, 2021, 2021 IEEE/ACM 7th Workshop on the LLVM Compiler Infrastructure in HPC (LLVM-HPC).

HAM: Hotspot-Aware Manager for Improving Communications With 3D-Stacked Memory

Antonino Tumeo, John D. Leidel, Xi Wang, 2021, IEEE Transactions on Computers.

xBGAS: A Global Address Space Extension on RISC-V for High Performance Computing

John D. Leidel, Michel A. Kinsy, Xi Wang, 2021, 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS).

DMM-GAPBS: Adapting the GAP Benchmark Suite to a Distributed Memory Model

John D. Leidel, Xi Wang, Brody Williams, 2021, 2021 IEEE High Performance Extreme Computing Conference (HPEC).

Extreme Heterogeneity 2018 - Productive Computational Science in the Era of Extreme Heterogeneity: Report for DOE ASCR Workshop on Extreme Heterogeneity

John D. Leidel, Jeremiah J. Wilke, Barbara M. Chapman, 2018 .

Toward a Memory-Centric , Stacked Architecture for Extreme-Scale , Data-Intensive Computing

John D. Leidel, Xi Wang, 2016 .

RaiderSTREAM: Adapting the STREAM Benchmark to Modern HPC Systems

John D. Leidel, Michael K Beebe, Yong Chen, 2022, 2022 IEEE High Performance Extreme Computing Conference (HPEC).

In-Memory Intelligence

John D. Leidel, Perry Lea, Glen Hush, 2017, IEEE Micro.

PIMS: a lightweight processing-in-memory accelerator for stencil computations

John D. Leidel, Jie Li, Antonino Tumeo, 2019, MEMSYS.