K. Tiri

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

P. Wambacq, M. Badaroglu, H.J. De Man, 2004, IEEE Journal of Solid-State Circuits.

Circuits and design techniques for secure ICs resistant to side-channel attacks

I. Verbauwhede, K. Tiri, D. Hwang, 2006, 2006 IEEE International Conference on IC Design and Technology.

AES-Based Security Coprocessor IC in 0.18-$muhbox m$CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

S. Yang, A. Hodjat, K. Tiri, 2006, IEEE Journal of Solid-State Circuits.

AES-based cryptographic and biometric security coprocessor IC in 0.18-/spl mu/m CMOS resistant to side-channel power analysis attacks

Bo-Cheng Lai, A. Hodjat, Shenglin Yang, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

Digital circuit capacitance and switching analysis for ground bounce in ICs with a high-ohmic substrate

H. De Man, G. Van der Plas, M. Badaroglu, 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards

I. Verbauwhede, K. Tiri, M. Akmal, 2002, Proceedings of the 28th European Solid-State Circuits Conference.

Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

H. De Man, M. Badaroglu, G. Gielen, 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).