Seong-Jin Jang

发表

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM

Dong-Hun Lee, Kiho Kim, Yong-Ho Cho, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface

Hong-June Park, Jung-Hwan Choi, Min-Kyun Chae, 2018, IEEE Journal of Solid-State Circuits.

A new column redundancy scheme for fast access time of 64-Mb DRAM

Young-Hyun Jun, Tae-Hoon Kim, Jong-Hoon Park, 1993, 1993 IEEE International Symposium on Circuits and Systems.

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Jae-Joon Song, Kyung-Soo Kim, Jongmin Kim, 2018, 2018 IEEE Symposium on VLSI Circuits.

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Hyun-Soo Park, Hyuk-Jun Kwon, Jong-Ho Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Junha Lee, Jung-Hwan Choi, Joon-Young Park, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Virtual fine delay line using one-stage inverter delay

Young-Hyun Jun, Soo-In Cho, Seong-Jin Jang, 2003 .

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme

Jun-Seok Park, Jongeun Lee, Kyomin Sohn, 2012, IEEE Journal of Solid-State Circuits.

5.7 A 29nW bandgap reference circuit

Byungsub Kim, Jae-Yoon Sim, Hong-June Park, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Jae-Hyung Lee, Young-Hyun Jun, Dae-Hyun Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

ASMD with duty cycle correction scheme for high-speed DRAM

Young-Hyun Jun, Jae-Goo Lee, Seong-Jin Jang, 2001 .

Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling

Hongzhong Zheng, Churoo Park, Seong-Jin Jang, 2014 .

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Jae-Wook Lee, Reum Oh, Dong-Hak Shin, 2016, ISSCC.

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

Jongmin Kim, Jung-Hwan Choi, Joon-Young Park, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Hyoung-Joo Kim, Jong-Ho Lee, Jun-Young Park, 2015, IEEE Journal of Solid-State Circuits.

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Yong-Jun Kim, Young-Sik Kim, Ju-Hwan Kim, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Hyun-Soo Park, Hyuk-Jun Kwon, Kyungbae Park, 2019, IEEE Journal of Solid-State Circuits.

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2011, IEICE Trans. Electron..

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Study on Knocking Analysis Simulator Based on CRDI Engine ECU

Jong-Wook Jang, Seong-Jin Jang, Hwa-seon Kim, 2012, FGIT-GDC/IESH/CGAG.

A study on scheduling algorithm for optimization of traffic distribution in MOST GATEWAY

Jong-Wook Jang, Seong-Jin Jang, 2011, The 17th Asia Pacific Conference on Communications.

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2010, 2010 Proceedings of ESSCIRC.

17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs

Jung-Hwan Choi, Seok-Ho Lee, Hundai Choi, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)

Yong-Hwan Kim, Jae-Hun Jung, Kyomin Sohn, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control

Yun-Sik Park, Soo-In Cho, Jongsoo Lee, 2004 .

A compact ring delay line for high speed synchronous DRAM

Young-Hyun Jun, Hoi-Jun Yoo, Seong-Ho Han, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

A study on traffic management methods in MOST GATEWAY system

Jong-Wook Jang, Seong-Jin Jang, 2011, ICTC 2011.

Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs

Reum Oh, Yun-Sang Lee, Byunghyun Lee, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Young Choi, Jung-Hwan Choi, Jongeun Lee, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Hoon Shin, Young Choi, Inkyu Moon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Development of the knocking decision system using the CKP signal collection and analysis

Jong-Wook Jang, Seong-Jin Jang, Hwa-seon Kim, 2014, Int. J. Secur. Networks.

Wave pipeline output circuit for synchronous memory device

Seong-Jin Jang, Joung-yeal Kim, 2006 .

A Study on Dynamic Gateway System for MOST GATEWAY Scheduling Algorithm in MOST25 and MOST150 Networks

Jong-Wook Jang, Seong-Jin Jang, 2011, ICHIT.

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

O Seongil, Jung Ho Ahn, Nam Sung Kim, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution

Reum Oh, Dong-Hak Shin, Jae-Hun Jung, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

An integrated circuit semiconductor device, the semiconductor device package and data processing system

Young-Hyun Jun, Seong-Jin Jang, Chang-Man Khang, 2002 .

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Woo-Jin Lee, Young-Hyun Jun, Jeong-Don Ihm, 2008, IEEE Journal of Solid-State Circuits.

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Sung Kyu Lim, Yarui Peng, Bon Woong Ku, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Young-Hyun Jun, Jeong-Don Ihm, Seung-Jun Bae, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.