Y. Hoshino

An embedded 0.405 /spl mu/m/sup 2/ stacked DRAM technology integrated with high-performance 0.2 /spl mu/m CMOS logic and 6-level metalization

M. Yoshida, H. Kawakami, K. Asaka, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

Photo induced toning mechanism in novel electrophotographic technology

M. Ozawa, Y. Hoshino, N. Tetsutani, 1990 .

Strained-silicon MOSFETs of low leakage current and high breakdown voltage for analog applications

Y. Hoshino, Y. Kondo, N. Sugii, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained Layer for low leakage current and high breakdown Voltage

Y. Hoshino, Y. Kondo, N. Sugii, 2006, IEEE Transactions on Electron Devices.

High performance scaled down Si LDMOSFET with thin gate bird's beak technology for RF power amplifiers

Y. Hoshino, Y. Matsunaga, S. Kamohara, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).