K. Tsuneno

An embedded 0.405 /spl mu/m/sup 2/ stacked DRAM technology integrated with high-performance 0.2 /spl mu/m CMOS logic and 6-level metalization

M. Yoshida, H. Kawakami, K. Asaka, 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

TCAD strategy for predictive VLSI memory development

H. Masuda, H. Sato, K. Tsuneno, 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

Applied TCAD in Mega-Bits Memory Design

Masayuki Nakamura, H. Sato, H. Masuda, 1993 .

TCAD diagnosis of I/O-pin latchup in scaled-DRAM

S. Narui, H. Masuda, H. Sato, 1996, 1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095).

TCAD-prototyping with new accurate worst-case definition for a 0.2 micron CMOS-ASIC process

H. Masuda, H. Sato, K. Tsuneno, 1999, 1999 4th International Workshop on Statistical Metrology (Cat. No.99TH8391).

Evaluation Of Two-dimensional Transient Enhanced Diffusion Of Phosphorus During Shallow Junction Formation

Hiroo Masuda, H. Sato, K. Tsuneno, 1993, [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD).

TCAD calibration framework for accurate prediction of scaled CMOS characteristics

H. Masuda, H. Sato, K. Tsuneno, 1997, 1997 2nd International Workshop on Statistical Metrology.

Device Simulator Calibration for Quartermicron CMOS Devices

Martin Knaipp, Siegfried Selberherr, Tibor Grasser, 1998 .

Accurate statistical process variation analysis for 0.25-/spl mu/m CMOS with advanced TCAD methodology

H. Masuda, K. Tsuneno, H. Kunitomo, 1998 .