C. C. Beh

A logic chip delay-test method based on system timing

Franco Motika, Nandakumar Nityananda Tendolkar, C. C. Beh, 1990 .

Do Stuck Fault Models Reflect Manufacturing Defects?

C. C. Beh, Charles E. Radke, E. Kofi Vida-Torku, 1982, ITC.

Improve Yield and Quality Through Testability Analysis of VLSI Circuits

C. C. Beh, Charles E. Radke, David M. Wu, 1984, ITC.