B. van Schravendijk

A low redeposition rate high density plasma CVD process for high aspect ratio 175 nm technology and beyond

T. Ivers, E. Kiewra, G. Papasouliotis, 1999, Proceedings of the IEEE 1999 International Interconnect Technology Conference (Cat. No.99EX247).

Cu electromigration improvement by adhesion promotion treatment (APT)

G. Dixit, T. Mountsier, G. Jiang, 2011, 2011 IEEE International Interconnect Technology Conference.

FSG process development for copper/damascene technology

J. D. Luttmer, T. Bonifield, J. West, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Highly Reliable Interface of Self-aligned CuSiN process with Low-k Sic barrier dielectric (k3.5) for 65nm node and beyond

T. Usami, M. Sekine, K. Ueno, 2006, 2006 International Interconnect Technology Conference.

Electromigration and Line R of Graphene Capped Cu Dual Damascene Interconnect

D. Edelstein, T. Nogami, S. Schmitz, 2021, International Electron Devices Meeting.

Interest of SiCO low k=4.5 spacer deposited at low temperature (400°C) in the perspective of 3D VLSI integration

C. Fenouillet-Béranger, R. Beneyton, J. Mazurier, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

In-situ Formation of a Copper Silicide Cap For TDDB and Electromigration Improvement

K. Chattopadhyay, B. van Schravendijk, T.W. Mountsier, 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.

Thin base formation by double diffused polysilicon technology

J.L. de Jong, B. van Schravendijk, P. Maillot, 1988, Proceedings of the 1988 Bipolar Circuits and Technology Meeting,.