Haralampos-G. D. Stratigopoulos

发表

Fault modeling and diagnosis for nanometric analog circuits

Salvador Mir, Ke Huang, Haralampos-G. D. Stratigopoulos, 2013, 2013 IEEE International Test Conference (ITC).

Analog neural network design for RF built-in self-test

He Huang, Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2010, 2010 IEEE International Test Conference.

Multidimensional analog test metrics estimation using extreme value theory and statistical blockade

Haralampos-G. D. Stratigopoulos, Pierre Faubet, Yoann Courant, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Statistical Approach to Characterizing and Testing Functionalized Nanowires

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, James Dardig, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

Practical Simulation Flow for Evaluating Analog/Mixed-Signal Test Techniques

Salvador Mir, Haralampos-G. D. Stratigopoulos, Manuel J. Barragan Asian, 2016, IEEE Design & Test.

Open Source Hardware and EDA Tools for Analog/Mixed-Signal Design and Prototyping

Naohiko Shimizu, Haralampos-G. D. Stratigopoulos, Junichi Akita, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Efficient Monte Carlo-based analog parametric fault modelling

Haralampos-G. D. Stratigopoulos, Stephen Sunter, H. Stratigopoulos, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Built-in test of millimeter-Wave circuits based on non-intrusive sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Special Session 7C: TTTC 2009 Best Doctoral Thesis Contest

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2009, 2009 27th IEEE VLSI Test Symposium.

Fault diagnosis of analog circuits based on machine learning

Salvador Mir, Ke Huang, Haralampos-G. D. Stratigopoulos, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Advances in variation-aware modeling, verification, and testing of analog ICs

Georges G. E. Gielen, Trent McConaghy, Haralampos-G. D. Stratigopoulos, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Enhanced reduced code linearity test technique for multi-bit/stage pipeline ADCs

Salvador Mir, Haralampos-G. D. Stratigopoulos, Asma Laraba, 2012, 2012 17th IEEE European Test Symposium (ETS).

Evaluation of low-cost mixed-signal test techniques for circuits with long simulation times

Salvador Mir, Haralampos-G. D. Stratigopoulos, Manuel J. Barragan Asian, 2015, 2015 IEEE International Test Conference (ITC).

An analog checker with input-relative tolerance for duplicate signals

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Hierarchical parametric test metrics estimation: A ΣΔ converter BIST case study

Salvador Mir, Haralampos-G. D. Stratigopoulos, Matthieu Dubois, 2009, 2009 IEEE International Conference on Computer Design.

Diagnosis of Local Spot Defects in Analog Circuits

Camelia Hora, Salvador Mir, Ke Huang, 2012, IEEE Transactions on Instrumentation and Measurement.

Special session 12A: Panel adaptive analog test: Feasibility and opportunities ahead

Haralampos-G. D. Stratigopoulos, 2010, VTS.

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

Salvador Mir, Haralampos-G. D. Stratigopoulos, Asma Laraba, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Adaptive Test With Test Escape Estimation for Mixed-Signal ICs

Haralampos-G. D. Stratigopoulos, Christian Streitwieser, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Guest Editorial

Krishnendu Chakrabarty, Haralampos-G. D. Stratigopoulos, 2011, J. Electron. Test..

Low-cost EVM built-in test of RF transceivers

Salvador Mir, Haralampos-G. D. Stratigopoulos, Ayssar Serhan, 2014, 2014 9th International Design and Test Symposium (IDT).

Sensors for built-in alternate RF test

Salvador Mir, Haralampos-G. D. Stratigopoulos, Louay Abdallah, 2010, 2010 15th IEEE European Test Symposium.

Non-RF to RF Test Correlation Using Learning Machines: A Case Study

Yiorgos Makris, Mustapha Slamani, Haralampos-G. D. Stratigopoulos, 2007, 25th IEEE VLSI Test Symposium (VTS'07).

Test Metrics Model for Analog Test Development

Haralampos-G. D. Stratigopoulos, H. Stratigopoulos, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Evaluation of Analog/RF Test Measurements at the Design Stage

Salvador Mir, Ahcène Bounceur, Haralampos-G. D. Stratigopoulos, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

One-shot calibration of rf circuits based on non-intrusive sensors

Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Martin Andraud, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Salvador Mir, Haralampos-G. D. Stratigopoulos, Manuel J. Barragan Asian, 2016, J. Electron. Test..

Solutions for the self-adaptation of communicating systems in operation

Salvador Mir, Michel Renovell, Haralampos-G. D. Stratigopoulos, 2014, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS).

On Replacing an RF Test with an Alternative Measurement: Theory and a Case Study

Salvador Mir, Haralampos-G. D. Stratigopoulos, Alexios Spyronasios, 2011, 2011 Asian Test Symposium.

An analog VLSI multilayer perceptron and its application towards built-in self-test in analog circuits

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Dzmitry Maliuk, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Recap of the European Test Symposium 2017 (ETS’17)

Maria K. Michael, Haralampos-G. D. Stratigopoulos, 2017, IEEE Design & Test.

Adaptive test flow for mixed-signal ICs

Haralampos-G. D. Stratigopoulos, Christian Streitwieser, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Self-Testing Analog Spiking Neuron Circuit

Bernabé Linares-Barranco, Haralampos-G. D. Stratigopoulos, Luis A. Camuñas-Mesa, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Density estimation for analog/RF test problem solving

Salvador Mir, Ahcène Bounceur, Haralampos-G. D. Stratigopoulos, 2010, VTS.

Fast Monte Carlo-Based Estimation of Analog Parametric Test Metrics

Haralampos-G. D. Stratigopoulos, Stephen Sunter, 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Testing RF circuits with true non-intrusive built-in sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Josep Altet, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Y. Makris, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Special session 8A: TTTC 2010 E. J. McCluskey Best Doctoral Thesis Award

Haralampos-G. D. Stratigopoulos, 2010, VTS.

Special session on machine learning: How will machine learning transform test?

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Amit Nahar, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

Defect filter for alternate RF test

Salvador Mir, Sule Ozev, Haralampos-G. D. Stratigopoulos, 2009, 2010 15th IEEE European Test Symposium.

A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio $\Sigma\Delta$ ADC

Salvador Mir, Haralampos-G. D. Stratigopoulos, Manuel J. Barragan Asian, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Reduced-Code Linearity Testing of Pipeline ADCs

Salvador Mir, Haralampos-G. D. Stratigopoulos, Asma Laraba, 2013, IEEE Design & Test.

Enrichment of limited training sets in machine-learning-based analog/RF test

Yiorgos Makris, Salvador Mir, Haralampos-G. D. Stratigopoulos, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

High frequency jitter estimator for SoCs

Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, 2015, 2015 20th IEEE European Test Symposium (ETS).

On proving the efficiency of alternative RF tests

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Petros Drineas, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

One-Shot Non-Intrusive Calibration Against Process Variations for Analog/RF Circuits

Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, Martin Andraud, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

True non-intrusive sensors for RF built-in test

Salvador Mir, Haralampos-G. D. Stratigopoulos, Louay Abdallah, 2013, 2013 IEEE International Test Conference (ITC).

Machine learning applications in IC testing

Haralampos-G. D. Stratigopoulos, H. Stratigopoulos, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Implicit test of high-speed analog circuits using non-intrusive sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Louay Abdallah, 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

ETS 2016 foreword

Giorgio Di Natale, Maria K. Michael, Haralampos-G. D. Stratigopoulos, 2016, ETS.

Bridging the accuracy of functional and machine-learning-based mixed-signal testing

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Y. Makris, 2006, 24th IEEE VLSI Test Symposium.

An analog checker with dynamically adjustable error threshold for fully differential circuits

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2003, Proceedings. 21st VLSI Test Symposium, 2003..

Fast deployment of alternate analog test using Bayesian model fusion

Xin Li, Yiorgos Tsiatouhas, Angela Arapoyanni, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Statistical Evaluation of Digital Techniques for $\sum\varDelta$ ADC BIST

Salvador Mir, Haralampos-G. D. Stratigopoulos, Manuel J. Barragan Asian, 2014, VLSI-SoC.

Concurrent detection of erroneous responses in linear analog circuits

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Y. Makris, 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Adaptive Alternate Analog Test

Salvador Mir, Haralampos-G. D. Stratigopoulos, H. Stratigopoulos, 2011, IEEE Design & Test of Computers.

Nonlinear decision boundaries for testing analog circuits

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Y. Makris, 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Yield forecasting in fab-to-fab production migration based on Bayesian Model Fusion

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Ali Ahmadi, 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Harnessing fabrication process signature for predicting yield across designs

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, Ali Ahmadi, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Special session 4C: Thesis research poster session

Haralampos-G. D. Stratigopoulos, 2010, VTS.

Multivariate statistical techniques for analog parametric test metrics estimation

Salvador Mir, Ke Huang, Ahcène Bounceur, 2013, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Experiences with non-intrusive sensors for RF built-in test

Salvador Mir, Haralampos-G. D. Stratigopoulos, Louay Abdallah, 2012, 2012 IEEE International Test Conference.

Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers

Alberto Valdes-Garcia, Haralampos-G. D. Stratigopoulos, 2012, IEEE Des. Test Comput..

A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation

Salvador Mir, Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, 2008, 2008 Design, Automation and Test in Europe.

RF Specification Test Compaction Using Learning Machines

Yiorgos Makris, Mustapha Slamani, Haralampos-G. D. Stratigopoulos, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Bayesian Fault Diagnosis of RF Circuits Using Nonparametric Density Estimation

Salvador Mir, Ke Huang, Haralampos-G. D. Stratigopoulos, 2010, 2010 19th IEEE Asian Test Symposium.

Defect-oriented non-intrusive RF test using on-chip temperature sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Josep Altet, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

MixLock: Securing Mixed-Signal Circuits via Logic Locking

Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos, Muhammad Yasin, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Guest Editors' Introduction: Top Papers from the 2015 International Test Conference

Haralampos-G. D. Stratigopoulos, Nicola Nicolici, 2016, IEEE Des. Test.

Generating decision regions in analog measurement spaces

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2005, GLSVLSI '05.

Test and Calibration of RF Circuits Using Built-in Non-intrusive Sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Emmanuel Simeu, 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

Concurrent error detection in linear analog circuits using state estimation

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Parametric Built-In Test for 65nm RF LNA Using Non-Intrusive Variation-Aware Sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Alexandre Siligaris, 2015, J. Electron. Test..

An Analog Checker with Input-Relative Tolerance for Duplicate Signals

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2004, J. Electron. Test..

Reduced code linearity testing of pipeline adcs in the presence of noise

Salvador Mir, Haralampos-G. D. Stratigopoulos, Asma Laraba, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Analog test metrics estimates with PPM accuracy

Salvador Mir, Haralampos-G. D. Stratigopoulos, H. Stratigopoulos, 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Evaluation of digital ternary stimuli for dynamic test of ΣΔ ADCs

Salvador Mir, Haralampos-G. D. Stratigopoulos, Manuel J. Barragan Asian, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Estimation of Analog Parametric Test Metrics Using Copulas

Salvador Mir, Ahcène Bounceur, Haralampos-G. D. Stratigopoulos, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Constructive derivation of analog specification test criteria

Yiorgos Makris, Haralampos-G. D. Stratigopoulos, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

RF Front-End Test Using Built-in Sensors

Salvador Mir, Haralampos-G. D. Stratigopoulos, Louay Abdallah, 2011, IEEE Design & Test of Computers.