Boryau Sheu

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains

Wen-Ben Jone, Shianling Wu, Xiaoqing Wen, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs

Michael S. Hsiao, Shianling Wu, Xiaoqing Wen, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction

Shianling Wu, Xiaoqing Wen, Boryau Sheu, 2005, IEEE International Conference on Test, 2005..

A Novel and Practical Control Scheme for Inter-Clock At-Speed Testing

Shianling Wu, Xiaoqing Wen, Hiroshi Furukawa, 2006, 2006 IEEE International Test Conference.

Test compression and logic BIST at your fingertips

Shianling Wu, Laung-Terng Wang, Boryau Sheu, 2005, IEEE International Conference on Test, 2005..

Turbo1500: Core-Based Design for Test and Diagnosis

Fangfang Li, Wen-Ben Jone, Shianling Wu, 2009, IEEE Design & Test of Computers.

VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG

Shianling Wu, Xiaoqing Wen, Xinli Gu, 2008, IEEE Design & Test of Computers.

Practical Challenges in Logic BIST Implementation – Case Studies

Shianling Wu, Hiroshi Furukawa, Laung-Terng Wang, 2008, 2008 17th Asian Test Symposium.

Hybrid Built-In Self-Test Architecture for Multi-port Static RAMs

Shianling Wu, Xiaoqing Wen, Laung-Terng Wang, 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.

Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard

Fangfang Li, Wen-Ben Jone, Shianling Wu, 2008, 2008 IEEE International Test Conference.