T. Grider

Effects of advanced processes on hot carrier reliability

V. McNeil, S. Aur, T. Holloway, 1998, 1998 IEEE International Reliability Physics Symposium Proceedings. 36th Annual (Cat. No.98CH36173).

A high performance 90 nm logic technology with a 37 nm gate length, dual plasma nitrided gate dielectric and differential offset spacer

P. Nicollian, J. Deloach, R. Khamankar, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Nickel SALICIDE technology for sub-100nm CMOS devices

D. Mercer, J. P. Lu, Donald S. Miles, 2004 .

Nickel SALICIDE Process Technology for CMOS Devices of 90nm Node and Beyond

Bill Y. Lin, T. Bonifield, F. Johnson, 2006, 2006 International Workshop on Junction Technology.

Program Disturb Mechanism in Embedded SuperFlash® Technology

Nhan Do, JinHo Kim, Jon Nafziger, 2020, 2020 IEEE International Reliability Physics Symposium (IRPS).

Advanced CMOS transistors with a novel HfSiON gate dielectric

H. Bu, R. Khamankar, T. Grider, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes

B. Hornung, C. Machala, A. Krishnan, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..