Keiji Takahisa

Validation of hardware error recovery mechanisms for the SPARC64 V microprocessor

Ryuji Kan, Yoshiharu Tosaka, Hisashige Ando, 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

Investigation of multi cell upset in sequential logic and validity of redundancy technique

Taiki Uemura, Takashi Kato, Hideya Matsuyama, 2011, 2011 IEEE 17th International On-Line Testing Symposium.

SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET

Keiji Takahisa, Kichiji Hatanaka, Yoshiharu Tosaka, 2010, 2010 IEEE International Reliability Physics Symposium.