Seshasayanan Ramachandran

Area and power efficient DCT architecture for image compression

Vaithiyanathan Dhandapani, Seshasayanan Ramachandran, 2014, EURASIP J. Adv. Signal Process..

An optimised twin precision multiplier for ASIC environment

Seshasayanan Ramachandran, Rosi Asirvatham, 2015, EURASIP J. Adv. Signal Process..

NULL Convention Floating Point Multiplier

Seshasayanan Ramachandran, Anitha Juliette Albert, 2015, TheScientificWorldJournal.