Yu-Po Cheng

An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits

Yen-Chi Chen, Soon-Jyh Chang, Yen-Long Lee, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Fast and Jitter-Modulation Free Jitter Tolerance Estimation Technique for Bang- Bang CDRs

Hsin-Wen Ting, Soon-Jyh Chang, Yen-Long Lee, 2018, IEEE Design & Test.

A 7 Gb/s half-rate clock and data recovery circuit with compact control loop

Soon-Jyh Chang, Yen-Long Lee, Yu-Po Cheng, 2016, 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).