A. Bandyopadhyay

A 80 /spl mu/W/frame 104/spl times/128 CMOS imager front end for JPEG compression

Abhishek Bandyopadhyay, Jungwon Lee, Paul E. Hasler, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 531 nW/MHz, 128/spl times/32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

Venkatesh Srinivasan, Abhishek Bandyopadhyay, Paul E. Hasler, 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

A CMOS floating-gate matrix transform imager

P. Hasler, D. Anderson, A. Bandyopadhyay, 2005, IEEE Sensors Journal.

Matrix Transform Imager Architecture for On-ChipLow-Power Image Processing

Abhishek Bandyopadhyay, A. Bandyopadhyay, 2004 .

Programming analog computational memory elements to 0.2% accuracy over 3.5 decades using a predictive method

Abhishek Bandyopadhyay, Paul E. Hasler, Guillermo J. Serrano, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A 120dB-SNR 100dB-THD+N 21.5mW/channel multibit CT ΔΣ DAC

Abhishek Bandyopadhyay, Khiem Nguyen, Michael Determan, 2011, 2011 IEEE International Solid-State Circuits Conference.

MATIA: a programmable 80 /spl mu/W/frame CMOS block matrix transform imager architecture

P. Hasler, A. Bandyopadhyay, Jungwon Lee, 2006, IEEE Journal of Solid-State Circuits.

A fully programmable CMOS block matrix transform imager architecture

Paul Hasler, A. Bandyopadhyay, P. Hasler, 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

A matrix transform imager and architecture

Paul Hasler, A. Bandyopadhyay, A. Bandyopadhyay, 2002, Proceedings of IEEE Sensors.

A matrix transform imager allowing high-fill factor

Abhishek Bandyopadhyay, Paul E. Hasler, Paul D. Smith, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).