Saichandrateja Radhapuram

ANALYSIS OF A CONTROLLER-BASED ALL-DIGITAL PHASE-LOCKED LOOP

Toshimasa Matsuoka, Weimin Wang, Ikkyun Jo, 2015 .

A low-voltage design of digitally-controlled oscillator based on the gm/ID methodology

Toshimasa Matsuoka, Takao Kihara, Ikkyun Jo, 2015, 2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT).

A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices

Toshimasa Matsuoka, Takao Kihara, Weimin Wang, 2016, IEICE Trans. Electron..

Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Toshimasa Matsuoka, Takuya Yoshihara, Saichandrateja Radhapuram, 2019 .

Erratum: Analysis of a Controller-Based All-Digital Phase-Locked Loop

Toshimasa Matsuoka, Weimin Wang, Ikkyun Jo, 2016 .

A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator

Toshimasa Matsuoka, Takao Kihara, Ikkyun Jo, 2015, IEICE Trans. Electron..

A low-power CMOS programmable frequency divider with novel retiming scheme

Toshimasa Matsuoka, Takao Kihara, Ikkyun Jo, 2015, IEICE Electron. Express.

A low-voltage design of controller-based ADPLL for implantable biomedical devices

Toshimasa Matsuoka, Takao Kihara, Ikkyun Jo, 2015, 2015 IEEE Biomedical Circuits and Systems Conference (BioCAS).

A Subthreshold Low-Voltage Low-Phase-Noise CMOS LC-VCO with Resistive Biasing

Toshimasa Matsuoka, Takao Kihara, Ikkyun Jo, 2015 .