Chang Wu

发表

Heterogeneous computing for CNN

Huizi Zhang, Chang Wu, Xiao Hu, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

A DEA-GA multi-objective scheduling algorithm for Chip-Multiprocessor

Jian Wang, Yubai Li, Chang Wu, 2013 .

A NoC Simulation and Verification Platform Based on SystemC

Yubai Li, Chang Wu, Song Chai, 2008, 2008 International Conference on Computer Science and Software Engineering.

Optimal FPGA mapping and retiming with efficient initial state computation

Jason Cong, Chang Wu, 1998, DAC.

Research and Implementation of Distributed Architecture of PACS

Chang Wu, 2001 .

Providing Useful Information for Passengers Based on TTF Model

Ye Tian, Chang Wu, Bo Yuan, 2014, 2014 IEEE International Conference on Internet of Things(iThings), and IEEE Green Computing and Communications (GreenCom) and IEEE Cyber, Physical and Social Computing (CPSCom).

A Reconfigurable Accelerator for Sparse Convolutional Neural Networks

Chang Wu, Weijie You, 2019, FPGA.

In-place LUT polarity inVersion to mitigate soft errors for FPGAs

Chang Wu, Lei He, Juexiao Su, 2016, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Global clustering-based performance-driven circuit partitioning

Jason Cong, Chang Wu, J. Cong, 2002, ISPD '02.

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip

Yubai Li, Chang Wu, Jian Wang, 2014, J. Comput..

Shortest path based simulated annealing algorithm for dynamic facility layout problem under dynamic business environment

Ming Dong, Chang Wu, Forest Hou, 2009, Expert Syst. Appl..

Performance driven multi-level and multiway partitioning with retiming

Jason Cong, Sung Kyu Lim, Chang Wu, 2000, Proceedings 37th Design Automation Conference.

Improving NOC performance through a new data-transfer technique

Jian Wang, Chang Wu, Yu BaiLi, 2007, 2007 7th International Conference on ASIC.

Design and simulation of a torus structure and route algorithm for network on chip

Yubai Li, Chang Wu, Song Chai, 2007, 2007 7th International Conference on ASIC.

An improved algorithm for performance optimal technology mapping with retiming in LUT-based FPGA design

Jason Cong, Chang Wu, 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

An analytical model for Network-on-Chip with finite input buffer

Yubai Li, Chang Wu, Jian Wang, 2011, Frontiers of Computer Science in China.

Lottery Router: A Customized Arbitral Priority NOC Router

Yubai Li, Chang Wu, Song Chai, 2008, 2008 International Conference on Computer Science and Software Engineering.

A Distributed Event-Triggered-Based Control Strategy and its Stability Analysis

Xing Zhang, Min Liu, Chang Wu, 2019, 2019 International Conference on Intelligent Transportation, Big Data & Smart City (ICITBS).

Highly Efficient Sparse Neural Network Computing: Hardware and Software Solutions

Jian Yu, Chang Wu, Chen Pan, 2019, FPGA.

Performance-driven fpga synthesis for sequential circuits

Jason Cong, Chang Wu, 1999 .

A Comparison of Genetic Algorithm, Particle Swarm Optimization and Simulated Annealing in Real-Time Task Scheduling on CMP

Jian Wang, Chang Wu, Song Chai, 2013 .

Design and verification of universal evaluation system for single event effect sensitivity measurement in very-large-scale integrated circuits

Chang Wu, Jun Yu, Tianqi Liu, 2019, IEICE Electron. Express.

Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only)

Wei Wu, Chien-Nan Jimmy Liu, Chang Wu, 2015, FPGA.

An efficient algorithm for performance-optimal FPGA technology mapping with retiming

Jason Cong, Chang Wu, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Resource and Data Optimization for Hardware Implementation of Deep Neural Networks Targeting FPGA-based Edge Devices

Chang Wu, Deming Chen, Xinheng Liu, 2018, 2018 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP).

A virtual orthogonal output direct digital frequency synthesizer design and implementation

Chang Wu, Chuang Bi, Zhong-wen Lan, 2007, 2007 7th International Conference on ASIC.

A Genetic Algorithm for Task Scheduling on NoC Using FDH Cross Efficiency

Jian Wang, Yubai Li, Chang Wu, 2013 .

FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuits

Jason Cong, Chang Wu, 1997, DAC.

Cut ranking and pruning: enabling a general and efficient FPGA mapping solution

Jason Cong, Chang Wu, Yuzheng Ding, 1999, FPGA '99.

Layout driven FPGA packing algorithm for performance optimization

Chang Wu, Lei He, GengSheng Chen, 2017, IEICE Electron. Express.

Simultaneous circuit partitioning/clustering with retiming for performance optimization

Jason Cong, Chang Wu, Honching Li, 1999, DAC '99.

Design of a Dual-Switching Mode NOC Router Microarchitecture

Chang Wu, Song Chai, Yu-bai Li, 2010, 2010 International Conference on Electrical and Control Engineering.

Optimal FPGA mapping and retiming with efficient initial state computation

Jason Cong, Chang Wu, 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..