José-Alejandro López Alcantud

VHDL-AMS modeling of self-organizing neural systems

José-Alejandro López Alcantud, Tom Kazmierski, T. Kazmierski, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem

Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, 2006, 2006 International Conference on Field Programmable Logic and Applications.

An Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks

Ramón Ruiz Merino, José Ángel Díaz-Madrid, José-Alejandro López Alcantud, 2009, IWANN.

A fourth order CMOS band pass filter for PIR sensors

Miguel Angel Domínguez, Ginés Doménech-Asensi, Juan Martínez-Alajarín, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

An all-hardware implementation of the subpixel refinement stage in SIFT algorithm

J. Javier Martínez-Álvarez, Ginés Doménech-Asensi, Ramón Ruiz Merino, 2018, Int. J. Circuit Theory Appl..

Description and Simulation of Bio-inspired Systems Using VHDL-AMS

Ginés Doménech-Asensi, Ramón Ruiz Merino, José-Alejandro López Alcantud, 2005, IWINAC.

An 11-bit 20-MSample/s pipelined ADC with OTA bias current regulation to optimize power dissipation

Ginés Doménech-Asensi, José Ángel Díaz-Madrid, José-Alejandro López Alcantud, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).