N. Shanbhag

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

R. Mooney, J.E. Jaussi, G. Balamurugan, 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

Instruction scheduling for low power on dynamically variable voltage processors

M.M. Mansour, N. Shanbhag, I. Hajj, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

Receiver adaptation and system characterization of an 8Gbps source-synchronous I/O link using on-die circuits in 0.13 /spl mu/m CMOS

R. Mooney, G. Balamurugan, D.R. Johnson, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).