K. Matsuda

Implementation and Evaluation for Circuit Partitioning with a Java-based High-Level Synthesis Tool

T. Miyoshi, S. Funada, K. Matsuda, 2015 .

A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme

Lee-Sup Kim, Takayasu Sakurai, M. Matsui, 1994 .

Verification Mechanism for Partitioned Circuits on a Java-based High Level Synthesizer with a Circuit Partiotioning Function

T. Miyoshi, S. Funada, K. Matsuda, 2016 .

Generation of the Verification Circuit by High-Level Synthesis Tool in a Circuit Partitioning mechanism

T. Miyoshi, S. Funada, K. Matsuda, 2014 .

A 0.8- mu m BiCMOS ATM switch on an 800 Mb/s asynchronous buffered banyan network

Sumio Tanaka, Kenji Maeguchi, Hiroyuki Hara, 1991 .

A 0.8 μm BiCMOS ATM switch on the 800 Mbps asynchronous buffered banyan network

H. Momose, M. Noda, S. Tanaka, 1990, Digest of Technical Papers., 1990 Symposium on VLSI Circuits.

200 MHz video compression macrocells using low-swing differential logic

Lee-Sup Kim, Takayasu Sakurai, Y. Uetani, 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

WP 4.6: 200MHz Video Compression Macrocells Using Low-Swing Differential Logic

Lee-Sup Kim, Yoshinori Watanabe, Takayasu Sakurai, 1992 .