Thomas Rinderknecht

High-frequency, at-speed scan testing

Janusz Rajski, Nagesh Tamarapalli, Bruce Swanson, 2003, IEEE Design & Test of Computers.

Embedded test for low cost manufacturing

Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, 2004, 17th International Conference on VLSI Design. Proceedings..

ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction

Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski, 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.

Logic BIST using constrained scan cells

Janak H. Patel, Wu-Tung Cheng, Liyang Lai, 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..

On the Generation of Compact Deterministic Test Sets for BIST Ready Designs

Sudhakar M. Reddy, Amit Kumar, Janusz Rajski, 2013, 2013 22nd Asian Test Symposium.

Signature Based Diagnosis for Logic BIST

Wu-Tung Cheng, Manish Sharma, Chris Hill, 2006, 2006 IEEE International Test Conference.

Logic BIST with scan chain segmentation

Janak H. Patel, Wu-Tung Cheng, Liyang Lai, 2004, 2004 International Conferce on Test.