Regis Leveugle

发表

Implementation of the Advanced Encryption Standard on GPUs with the NVIDIA CUDA framework

Paolo Maistri, Florian Masson, Regis Leveugle, 2011, 2011 IEEE Symposium on Industrial Electronics and Applications.

Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results

Regis Leveugle, Lorena Anghel, J. Ferron, 2011 .

Ensuring High Testability without Degrading Security

Giorgio Di Natale, Regis Leveugle, Bruno Rouzeyre, 2009, ETS 2009.

Integrated systems security: hardware-based threats and solutions

Regis Leveugle, 2010 .

Alternatives to Fault Injections for Early Safety/Security Evaluations

Alessandro Savino, Giorgio Di Natale, Alberto Bosio, 2019, 2019 IEEE European Test Symposium (ETS).

A channelless layout for multilevel synthesis with compiled cells

Regis Leveugle, G. Saucier, P. Abouzeid, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

Upset-like fault injection in VHDL descriptions: A method and preliminary results

Regis Leveugle, Raoul Velazco, O. Calvo, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Taking care of security in hardware design

Regis Leveugle, R. Leveugle, 2011 .

Design and validation of dependable integrated systems

Regis Leveugle, 2006 .

Evaluating soft error effects using probabilistic testability analysis: a case study

Regis Leveugle, P. Vanhauwaert, 2008 .

Concurrent checking in dedicated controllers

Regis Leveugle, G. Saucier, 1989, Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks

Vincent Beroulle, Regis Leveugle, Athanasios Papadimitriou, 2014, DATE 2014.

Defect and Fault Tolerance in VLSI Systems

Glenn H. Chapman, Regis Leveugle, 2003 .

Early dependability evaluation: injection of multiple bit-flips

Regis Leveugle, K. Hadjiat, 2005 .

Co-designed accelerator for homomorphic encryption applications

Rached Tourki, Regis Leveugle, P. Maistri, 2018 .

10th IEEE International On-Line Testing Symposium

Cecilia Metra, Regis Leveugle, Michael Nicolaidis, 2004 .

Extended Duplex Fault Tolerant System With Integrated Control Flow Checking

Regis Leveugle, G. Saucier, X. Delord, 1990 .

Dynamic Authentication-Based Secure Access to Test Infrastructure

Regis Leveugle, Michele Portolan, Vincent Reynaud, 2020, 2020 IEEE European Test Symposium (ETS).

On-Line Test and Fault Tolerance

Cecilia Metra, Regis Leveugle, C. Metra, 2005 .

Analyse du comportement des circuits asynchrones en présence de fautes

Regis Leveugle, Marc Renaudin, Y. Monnet, 2005 .

Efficiency comparison of signature monitoring schemes for FSMs

Regis Leveugle, G. Saucier, R. Rochet, 1995, Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair.

A CHANNELIZSS LAYOUT FOR MUL'DLEWEL SYNTHESIS WITH COMPILED CELLS

Regis Leveugle, G. Saucier, P. Abouzeid, 1989 .

Tools and methodology development for pulsed laser fault injection in SRAM-based FPGAs

Lorena Anghel, Regis Leveugle, J. Ferron, 2007 .

FPGA emulation of laser attacks against secure deep submicron integrated circuits

Vincent Beroulle, Paolo Maistri, Regis Leveugle, 2013 .

Injection of multiple bit-flips for counter measures validation

Regis Leveugle, K. Hadjiat, A. Ammari, 2005 .

An application specific microprocessor with two-level built-in control flow checking capabilities

Regis Leveugle, T. Michel, F. Gaume, 1992, Proceedings Euro ASIC '92.

Integrated and embedded systems security: hardware-based threats and solutions

Regis Leveugle, 2009 .

A Novel Double-Data-Rate AES Architecture Resistant against Fault Injection

Regis Leveugle, P. Maistri, P. Vanhauwaert, 2007 .

Design methodology of FSMs with intrinsic fault tolerance and recovery capabilities

Regis Leveugle, L. Martinez, 1992, Proceedings Euro ASIC '92.

Configuration errors analysis in SRAM-based FPGAs

Regis Leveugle, J. Ferron, Vincent Pouget, 2007 .

Fast register criticality evaluation in a SPARC microprocessor

Regis Leveugle, Michele Portolan, Kais Chibani, 2014, 2014 10th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).

ASYL-SdF: A Synthesis Tool for Dependability in Controllers (Special Issue on Synthesis and Verification of Hardware Design)

Regis Leveugle, G. Saucier, Raphael Rochet, 1996 .

A solution to test design bottleneck

Regis Leveugle, G. Saucier, M. Karam, 1992 .

Early analysis of fault-attack effects for cryptographic hardware

Regis Leveugle, R. Leveugle, 2004 .

A new automated instrumentation for emulation-based fault injection

Regis Leveugle, Adrien Prost-Boucle, 2010, 2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS).

Soft Error Effect and Register Criticality Evaluations: Past, Present and Future

Laurence Pierre, Regis Leveugle, Renaud Clavel, 2009 .

Synthesis of decision diagrams from clock-driven multi-process VHDL descriptions for test generation

Raimund Ubar, Regis Leveugle, 1999 .

Software-based BIST capabilities of the Advanced Encryption Standard

Regis Leveugle, P. Maistri, C. Excoffon, 2008, ETS 2008.

Datapath implementation: bit-slice structure versus standard cells

Regis Leveugle, P. Magarshack, L. Sponga, 1992, Proceedings Euro ASIC '92.

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Targeting approximation through data lifetime: a quest for optimization metrics

Alessandro Savino, Regis Leveugle, Michele Portolan, 2019 .

Design & Test of Integrated Systems in Nanoscale Technology

Regis Leveugle, 2006 .

Approximate computing design exploration through data lifetime metrics

Alessandro Savino, Stefano Di Carlo, Regis Leveugle, 2019, 2019 IEEE European Test Symposium (ETS).

Experimental Assessment of Cache Memory Soft Error Rate Prediction Technique

Thomas Santini, Florent Miller, Regis Leveugle, 2012, IEEE Transactions on Nuclear Science.

Statistical fault injection: how much is sufficient?

Regis Leveugle, P. Maistri, P. Vanhauwaert, 2008 .

SET fault injection methods in analog circuits: case study

Lorena Anghel, Regis Leveugle, Cristiano Lazzari, 2007 .

Reconfiguration in a microprocessor: practical results

Regis Leveugle, J. Trilhe, 1990 .

Behavior modeling of faulty complex VLSIs: why and how?

Regis Leveugle, 1998 .

Natural and malicious soft errors: dependability and security issues in ASICs and reconfigurable platforms

Regis Leveugle, 2013 .

Experimental evaluation of protections against laser-induced faults and consequences on fault modeling

Assia Tria, Regis Leveugle, Jean-Baptiste Rigaud, 2007 .

Integrated circuit with peripheral inspection control

Regis Leveugle, Patrick Lestrat, 1991 .

System-level dependability analysis with RT-level fault injection accuracy

Regis Leveugle, D. Cimonnet, A. Ammari, 2004 .

Injections de fautes transitoires dans une PLL

Regis Leveugle, A. Ammari, 2004 .

Natural and malicious soft errors: dependability and security issues in reconfigurable platforms

Regis Leveugle, 2011, ReCoSoC 2011.

Réalisation d'une tolérance aux fautes à bas coût dans les SoCs en utilisant le système d'exploitation

Regis Leveugle, Michele Portolan, 2004 .

Defect Tolerance in a 16-Bit Microprocessor

Norbert Wehn, Regis Leveugle, Mohammad Soueidan, 1989 .