Yoichi Tamaki

FOREWORD (Special Issue on Microelectronic Test Structure)

Yoichi Tamaki, 1996 .

New Test Structures for Evaluating the Scaling Limit of a Narrow U-Groove Isolation Structure

Yoichi Tamaki, Takashi Hashimoto, 1999 .

29 ps ECL circuits using U-groove isolated SICOS technology

Yoichi Tamaki, Tokuo Kure, Takashi Kobayashi, 1989, International Technical Digest on Electron Devices Meeting.

by using test structures

Yoichi Tamaki, Takayuki Iwasaki, Kousuke Tsuji, 2001 .

New test structure for evaluating low-k dielectric interconnect layers by using ring-oscillators and metal comb/serpentine patterns

Yoichi Tamaki, Yoshifumi Kawamoto, Yoshio Takimoto, 2011, 2011 IEEE ICMTS International Conference on Microelectronic Test Structures.

A 100 nm emitter transistor fabricated with direct EB writing for high-speed bipolar LSIs

Yoichi Tamaki, Fumio Murai, Akio Anzai, 1987, 1987 Symposium on VLSI Technology.

A 0.5- mu m very-high-speed silicon bipolar devices technology U-groove-isolated SICOS

Yoichi Tamaki, Tokuo Kure, Takeo Shiba, 1991 .

Evaluation of Dislocation Generation in Silicon Substrates by Selective Oxidation of U‐Grooves

Yoichi Tamaki, Masao Kawamura, Kazuhiko Sagara, 1987 .

Evaluation of Dislocation Generation in U‐Groove Isolation

Yoichi Tamaki, Tokuo Kure, Masao Kawamura, 1988 .

U-Groove Isolation Technology for High Density Bipolar LSI's

Yoichi Tamaki, Tokuo Kure, Hisayuki Higuchi, 1982 .

Ultra-small high-speed bipolar transistor with sidewall silicide technology

Yoichi Tamaki, Noriyuki Homma, Takahiro Onai, 1991, Proceedings of the 1991 Bipolar Circuits and Technology Meeting.