Shigetoshi Wakayama

Receiver circuit for use in a signal transmission system

Hirotaka Tamura, Junji Ogawa, Miyoshi Saito, 1997 .

Timer circuit, device and system for semiconductor integrated circuit under their application and signal transmission system

Hirotaka Tamura, Junji Ogawa, Shigetoshi Wakayama, 1998 .

A fer Amplifier an Encoded Bus Amhikc ower S

Toshihiko Mori, Shigetoshi Wakayama, Makoto Hamaminato, 1997 .

High-speed DRAM

Junji Ogawa, Toshiya Nishi, Takaaki Suzuki, 1998 .

A Charge-Transfer-Amplifier and an Encoded-Bus Architecture for Low-Power SRAM's

Toshihiko Mori, Shigetoshi Wakayama, Makoto Hamaminato, 1997 .

10-ns row cycle DRAM using temporal data storage buffer architecture

Hirotaka Tamura, Junji Ogawa, Miyoshi Saito, 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).