Sumit Ahuja

发表

System Level Simulation Guided Approach for Clock-Gating

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2011 .

High Level Simulation Directed RTL Power Estimation

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Architectural Selection Using High Level Synthesis

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Statistical Regression Based Power Models

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Accurate power estimation of hardware co-processors using system level simulation

Sandeep K. Shukla, Deepak Mathaikutty, Sumit Ahuja, 2009, 2009 IEEE International SOC Conference (SOCC).

VT Matrix Multiply Design for MEMOCODE '07

Sandeep K. Shukla, Patrick Schaumont, Sumit Ahuja, 2007, 2007 5th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2007).

Model-Checking to Exploit Sequential Clock-Gating

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Assertion-Based Modal Power Estimation

Sandeep K. Shukla, Deepak Mathaikutty, Sumit Ahuja, 2007, 2007 Eighth International Workshop on Microprocessor Test and Verification.

Power Reduction Using High-Level Clock-Gating

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Regression-Based Dynamic Power Estimation for FPGAs

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2012 .

Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications

Sandeep K. Shukla, S. S. Ravi, Gaurav Singh, 2007, Power-aware Computing Systems.

Power Aware High Level Synthesis of Hardware Coprocessors

Wei Zhang, Sandeep K. Shukla, Sumit Ahuja, 2010, J. Low Power Electron..

High Level Power Estimation and Reduction Techniques for Power Aware Hardware Design

Sumit Ahuja, Sumit Ahuja, 2010 .

Fault‐ and Defect‐Tolerant Architectures for Nanocomputing

Sandeep K. Shukla, Gaurav Singh, D. Bhaduri, 2009 .

FPGA Implementation of Directional Relays

D. N. Vishwakarma, Sumit Ahuja, S. K. Balasubramanian, 2005 .

System level simulation guided approach to improve the efficacy of clock-gating

Wei Zhang, Sandeep K. Shukla, Sumit Ahuja, 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

Hardware Coprocessor Synthesis from an ANSI C Specification

Sandeep K. Shukla, Swathi T. Gurumani, Sumit Ahuja, 2009, IEEE Design & Test of Computers.

High Level Power Estimation Models for FPGAs

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2011, 2011 IEEE Computer Society Annual Symposium on VLSI.

Coprocessor design space exploration using high level synthesis

Sandeep K. Shukla, Sumit Ahuja, Avinash Lakshminarayana, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Model-driven test generation for system level validation

Sandeep K. Shukla, Deepak Mathaikutty, Sumit Ahuja, 2007, 2007 IEEE International High Level Design Validation and Test Workshop.

SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation

Sandeep K. Shukla, Deepak Mathaikutty, Sumit Ahuja, 2009, J. Low Power Electron..

Power estimation methodology for a high-level synthesis framework

Sandeep K. Shukla, Deepak Mathaikutty, Gaurav Singh, 2009, 2009 10th International Symposium on Quality Electronic Design.

Applying Verification Collaterals for Accurate Power Estimation

Sandeep K. Shukla, Deepak Mathaikutty, Sumit Ahuja, 2008, 2008 Ninth International Workshop on Microprocessor Test and Verification.

DRUM : une unité reconfigurable intégrée sur plateforme multiprocesseurs hétérogène

Bernard Pottier, Erwan Fabiani, Love Kothari, 2003 .

A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms

Wei Zhang, Sandeep K. Shukla, Sumit Ahuja, 2010, 2010 23rd International Conference on VLSI Design.

The Model Checking View to Clock Gating and Operand Isolation

Sandeep K. Shukla, Klaus Schneider, Jens Brandt, 2010, 2010 10th International Conference on Application of Concurrency to System Design.

Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications

Sandeep K. Shukla, Gaurav Singh, Sumit Ahuja, 2007, J. Low Power Electron..

MCBCG: Model Checking Based Sequential Clock-Gating

Sandeep K. Shukla, Sumit Ahuja, 2009, 2009 IEEE International High Level Design Validation and Test Workshop.

SPAF : A System-level Power Analysis Framework

Gaurav Singh, Sumit Ahuja, Ajit Dingankar, 2007 .