Hikaru Hida

发表

A low-noise low-IF 0.18μm CMOS receiver IC with an active on-chip channel-selection filter for 5GHz wireless applications

Hitoshi Yano, Shinichi Hori, Tadashi Maeda, 2002 .

Low power consumption 16:1 MUX/DMUX for the STM-16 transmission systems based on DMT DCFL circuits

Tadashi Maeda, Masahiro Fujii, Hikaru Hida, 1992 .

A high-speed low-power tri-state driver flip flop for ultra-low supply voltage GaAs heterojunction FET LSI's

Tadashi Maeda, K. Numata, Hikaru Hida, 1996 .

A 0.04 cc Power Amplifier Module with Fully Integrated Passives in a Hybrid LTCC Substrate for 5-GHz Wireless LANs

Hikaru Hida, Masahiro Fujii, Kazuaki Kunihiro, 2002, 2002 32nd European Microwave Conference.

10 Gbit/s optical transmitter module with MQW DFB-LD and DMT driver IC

Sadao Fujita, Hikaru Hida, Hirohito Yamada, 1990 .

Sub-1 V supply voltage GaAs LSI technology based on 0.25 μm E/D-HJFETs (IS3Ts)

Tadashi Maeda, K. Numata, Hikaru Hida, 1995 .

A high-power-handling GSM switch IC with new adaptive-control-voltage-generator circuit scheme

Tadashi Maeda, K. Numata, Y. Takahashi, 2003, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003.

0.6 V suppy voltage 0.25 /spl mu/m E/D-HJFET(IS/sup 3/T) LSI technology for low power consumption and high speed LSIs

Tadashi Maeda, K. Numata, Hikaru Hida, 1993, 15th Annual GaAs IC Symposium.

0.6V supply voltage 0.25 μm E/D-HJFET(IS3T) LSI technology for low power consumption and high speed LSIs

Tadashi Maeda, Hikaru Hida, Muneo Fukaishi, 1993 .

High-speed and large noise margin tolerance E/D logic gates with LDD structure DMTs fabricated using selective RIE technology

Hikaru Hida, H. Toyoshima, Y. Tsukada, 1989 .

WLAN CMOS Transceiver

Hitoshi Yano, Shinichi Hori, Tadashi Maeda, 2005 .

A technique for compensating for temperature variation in low-supply-voltage GaAs DCFL circuits

Tadashi Maeda, K. Numata, Hikaru Hida, 1996 .

High-speed low-power tri-state driver flip-flop for sub-1 V supply voltage GaAs heterojunction FET LSIs

Tadashi Maeda, K. Numata, Hikaru Hida, 1995 .

A 1. 3 V supply voltage AIGaAs/lnGaAs HJFET SCFL D-FF operating at up to 10 gbps

Tadashi Maeda, Masahiro Fujii, Hikaru Hida, 1996 .

Effect of gain expansion on power HBTs

Noriaki Matsuno, Hikaru Hida, Yasuyuki Suzuki, 2000, 2000 30th European Microwave Conference.

0.2-/spl mu/m fully-self-aligned Y-shaped gate HJFET's with reduced gate-fringing capacitance fabricated using collimated sputtering and electroless Au-plating

Hitoshi Yano, Tadashi Maeda, Noriaki Matsuno, 1998 .

A 10-Gbit/s laser driver IC with i-AlGaAs/n-GaAs doped-channel hetero-MISFETs (DMTs)

Hikaru Hida, T. Suzaki, S. Fujita, 1989, 11th Annual Gallium Arsenide Integrated Circuit (GaAs IC) Symposium.

"A sub-0.25/spl mu/m symmetric super self-aligned gate hjfet witn reduced gate fringing capacitance fabricated using electroless au plating and collimated sputtering"

Hitoshi Yano, Noriaki Matsuno, Hikaru Hida, 1994, 52nd Annual Device Research Conference.