S. Ohbayashi

A high performance 0.6 mu m BiCMOS SRAM technology with emitter-base self-aligned bipolar transistors and retrograde well for MOS transistors

Toru Shiomi, Shigeki Ohbayashi, Yoshiyuki Ishigaki, 1992, 1992 Symposium on VLSI Technology Digest of Technical Papers.

A 45nm 0.6V cross-point 8T SRAM with negative biased read/write assist

M. Yabuuchi, K. Nii, Y. Tsukamoto, 2009, 2009 Symposium on VLSI Circuits.

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

K. Ishibashi, M. Yabuuchi, H. Makino, 2007, IEEE Journal of Solid-State Circuits.

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

M. Yabuuchi, H. Makino, K. Nii, 2009, IEEE Journal of Solid-State Circuits.

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

T. Iwasaki, M. Yabuuchi, K. Usui, 2008, 2008 IEEE Symposium on VLSI Circuits.

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

M. Yabuuchi, T. Terano, H. Makino, 2008, IEEE Journal of Solid-State Circuits.

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.