K. Tran

A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor

S. Dhong, C. Jacobi, H. Oh, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

The use of a WLR technique to characterize voiding in 0.25 and 0.18 /spl mu/m technologies for integrated circuits

P. Besser, A. Marathe, P. Fang, 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

The era of high bandwidth memory

Kevin Tran, K. Tran, 2016, 2016 IEEE Hot Chips 28 Symposium (HCS).

Scaling the Next-Generation Architecture: The Integration of 2.5D and 3D Integrated Circuits

Kevin Tran, K. Tran, 2016, IEEE Solid-State Circuits Magazine.

Thermal Performance of Double-Sided Metal Core PCBs

G. Holt, M. Pelletier, J. Wanjura, 2019, AgriEngineering.