Peter Zipf

发表

Design and Development of a Supported Tiered Software for Teaching and Learning Using a Connected Mobile Learning Application

Tze Ying Sim, Sian Lun Lau, Peter Zipf, 2014 .

Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs"

Peter Zipf, Martin Kumm, 2016, Int. J. Reconfigurable Comput..

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling

Martin Kumm, Peter Zipf, Patrick Sittel, 2019, 2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

FIR filter optimization for video processing on FPGAs

Peter Zipf, Martin Kumm, Diana Fanghänel, 2013, EURASIP J. Adv. Signal Process..

A multichannel high-resolution (<5 ps RMS between two channels) Time-to-Digital Converter (TDC) implemented in a field programmable gate array (FPGA)

Peter Zipf, Eugen Bayer, Michael Traxler, 2011, 2011 IEEE Nuclear Science Symposium Conference Record.

Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream

Michel Renovell, Peter Zipf, Manfred Glesner, 2002, Lecture Notes in Computer Science.

Efficient Error-Tolerant Quantized Neural Network Accelerators

Martin Kumm, Peter Zipf, Michaela Blott, 2019, 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Generation of Synthetic Floating-Point benchmark circuits

Philip Heng Wai Leong, Manfred Glesner, Peter Zipf, 2009, 2009 IEEE International Symposium on Parallel & Distributed Processing.

Pipelined reconfigurable multiplication with constants on FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A configurable pipelined state machine as a hybrid ASIC and configurable architecture

Manfred Glesner, Peter Zipf, Claude Stötzler, 2004, IEEE Computer Society Annual Symposium on VLSI.

Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Efficient structural adder pipelining in transposed form FIR filters

Mathias Faust, Chip-Hong Chang, Peter Zipf, 2015, 2015 IEEE International Conference on Digital Signal Processing (DSP).

Systems on a Chip

Manfred Glesner, Peter Zipf, M. Glesner, 2004 .

Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks

Ulrich Heinkel, Manfred Glesner, Tudor Murgan, 2005, ReCoSoC.

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

Kong-Pang Pun, Philip Heng Wai Leong, Manfred Glesner, 2004, FPL.

An area-efficient FPGA realisation of a codebook-based image compression method

Hui Shao, Radu Dogaru, Manfred Glesner, 2008, 2008 International Conference on Field-Programmable Technology.

A hierarchical generic approach for on-chip communication, testing and debugging of SoCs

Manfred Glesner, Peter Zipf, Christoph Mager, 2003, VLSI-SOC.

Hybrid multiple constant multiplication for FPGAs

Peter Zipf, Martin Kumm, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

A Concept for a Profile-based Dynamic Reconfiguration Mechanism

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2006, ReCoSoC.

The XPP Architecture and Its Co-simulation Within the Simulink Environment

Manfred Glesner, Tudor Murgan, Mihail Petrov, 2004, FPL.

Dynamic power optimization of the trace-back process for the Viterbi algorithm

Manfred Glesner, Tudor Murgan, Mihail Petrov, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures

Alberto García Ortiz, Manfred Glesner, Tudor Murgan, 2003, FPL.

High speed low complexity FPGA-based FIR filters using pipelined adder graphs

Peter Zipf, Martin Kumm, 2011, 2011 International Conference on Field-Programmable Technology.

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips

Pascal Benoit, Manfred Glesner, Peter Zipf, 2009, Int. J. Reconfigurable Comput..

A switch architecture and signal synchronization for GALS system-on-chips

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications

Manfred Glesner, Michel Renovell, Peter Zipf, 2002 .

Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme)

Manfred Glesner, Peter Zipf, Thilo Pionteck, 2007, it Inf. Technol..

Arbitrary function approximation in HDLs with application to the N-body problem

Philip Heng Wai Leong, Alberto García Ortiz, Manfred Glesner, 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).

Optimal Single Constant Multiplication Using Ternary Adders

Peter Zipf, Martin Kumm, Oscar Gustafsson, 2018, IEEE Transactions on Circuits and Systems II: Express Briefs.

Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits

Peter Zipf, Martin Kumm, Mario Garrido, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays

Peter Zipf, P. Zipf, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Dynamically reconfigurable FIR filter architectures with fast reconfiguration

Peter Zipf, Martin Kumm, Konrad Möller, 2013, 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC).

On a hardware architecture for the evolution of cellular automata functionality

Radu Dogaru, Peter Zipf, Manfred Glesner, 2005, ISSCS 2005.

A hardware-in-the-loop system to evaluate the performance of small-world cellular automata

Radu Dogaru, Manfred Glesner, Clemens Schlachta, 2005, International Conference on Field Programmable Logic and Applications, 2005..

Real-time fetal ECG system design using embedded microprocessors

Uwe Meyer-Baese, Peter Zipf, Martin Kumm, 2016, Commercial + Scientific Sensing and Imaging.

A Power Estimation Model for an FPGA-Based Softcore Processor

Lei Deng, Manfred Glesner, Holger Blume, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Functional modeling techniques for a wireless LAN OFDM transceiver

Manfred Glesner, Tudor Murgan, Peter Zipf, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC

Manfred Glesner, Peter Zipf, Michael Velten, 2005, GI Jahrestagung.

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2019, FPGA.

A Customizable LEON2-Based VLIW Processor

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2007, ReCoSoC.

Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits pdf

Peter Zipf, Martin Kumm, Konrad Möller, 2015, ArXiv.

Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen

Manfred Glesner, Peter Zipf, Yang Qiao, 2007, MBMV.

Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing

Ulrich Heinkel, Manfred Glesner, Tudor Murgan, 2004, CF '04.

Coarse-grained reconfiguration.

Jürgen Teich, Julio A. de Oliveira Filho, Wolfgang Rosenstiel, 2008, FPL 2008.

CONAN - a design exploration framework for reliable nano-electronics architectures

Yusuf Leblebici, Adrian M. Ionescu, Alexandre Schmid, 2005, 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05).

Flexible Overhead Processing Architectures for G.709 Optical Transport Networks

Ulrich Heinkel, Manfred Glesner, Tudor Murgan, 2004, MBMV.

Multitasking Support for Dynamically Reconfig Urable Systems

Leandro Soares Indrusiak, Manfred Glesner, Peter Zipf, 2006, 2006 International Conference on Field Programmable Logic and Applications.

Eine Scheduling Heuristik zur Minimierung der Verlustleistung

Manfred Glesner, Peter Zipf, Thilo Pionteck, 2006, MBMV.

Reduced complexity single and multiple constant multiplication in floating point precision

Peter Zipf, Martin Kumm, Katharina Liebisch, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits

Manfred Glesner, Tudor Murgan, Peter Zipf, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Dynamically Reconfigurable Systems for Wireless Sensor Networks

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2010, Dynamically Reconfigurable Systems.

Integration und Fehlertoleranz im Codesign

Peter Zipf, Hans Wojtkowiak, Christine Bauer, 2000, MBMV.

ILP-Based Modulo Scheduling and Binding for Register Minimization

Peter Zipf, Martin Kumm, Andreas Koch, 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

A model-based development approach for multi-cavity RF control systems

Manfred Glesner, Peter Zipf, Pongyupinpanich Surapong, 2009 .

Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension

Manfred Glesner, Peter Zipf, Hans Wojtkowiak, 2002, FPL.

An asynchronous switch implementation for systems-on-a-chip

Peter Zipf, Manfred Glesner, Thomas Hollstein, 2004 .

A metric for the energy-efficiency of dynamically reconfigurable systems

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2006, ARCS Workshops.

Integration monolithischer CMOS Schaltungen für Mobilfunkanwendungen : Entwurfsmethoden und Herausforderungen

Manfred Glesner, Peter Zipf, Thilo Pionteck, 2002 .

Towards a unique FPGA-based identification circuit using process variations

Philip Heng Wai Leong, Manfred Glesner, Haile Yu, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Efficient sum of absolute difference computation on FPGAs

Peter Zipf, Martin Kumm, Marco Kleinlein, 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

System design challenge s in the nanoscale era

Manfred Glesner, Tudor Murgan, Peter Zipf, 2007 .

Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model

Manfred Glesner, Peter Zipf, Claude Stötzler, 2005, ReCoSoC.

Reconfigurable platforms for ubiquitous computing

Leandro Soares Indrusiak, Manfred Glesner, Tudor Murgan, 2004, CF '04.

SPP1148 booth: Coarse-grained reconfiguration

Jürgen Teich, Julio A. de Oliveira Filho, Wolfgang Rosenstiel, 2008, 2008 International Conference on Field Programmable Logic and Applications.

Implementation of Realtime and Highspeed Phase Detector on FPGA

Manfred Glesner, Peter Zipf, Martin Kumm, 2006, ARC.

Design Optimisations for a Cellular Automata Model with Programmable Interconnect Structure

Lei Liu, Zdravko Bozakov, Peter Zipf, 2007 .

Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II

Manfred Glesner, Peter Zipf, Harald Klingbeil, 2008, 2008 The 19th IEEE/IFIP International Symposium on Rapid System Prototyping.

Karatsuba with Rectangular Multipliers for FPGAs

Florent de Dinechin, Peter Zipf, Martin Kumm, 2018, 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH).

Unrolling Ternary Neural Networks

Peter Zipf, Martin Kumm, David Boland, 2019, ACM Trans. Reconfigurable Technol. Syst..

Pipelined adder graph optimization for high speed multiple constant multiplication

Mathias Faust, Chip-Hong Chang, Peter Zipf, 2012, 2012 IEEE International Symposium on Circuits and Systems.

SPP1148 booth: Application-specific reconfigurable processors

Norbert Wehn, Manfred Glesner, Peter Zipf, 2008, 2008 International Conference on Field Programmable Logic and Applications.

ScaLP: A Light-Weighted (MI)LP-Library

Peter Zipf, Martin Kumm, Patrick Sittel, 2018, MBMV.

An Asynchronous Switch Implmentation for Systems-on-a-Chip

Manfred Glesner, Peter Zipf, Thomas Hollstein, 2004, MBMV.

Resource Optimal Design of Large Multipliers for FPGAs

Peter Zipf, Martin Kumm, Matei Istoan, 2017, 2017 IEEE 24th Symposium on Computer Arithmetic (ARITH).

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2009, 2009 International Conference on Field Programmable Logic and Applications.

Optimization of Constant Matrix Multiplication with Low Power and High Throughput

Peter Zipf, Martin Kumm, Martin Hardieck, 2017, IEEE Transactions on Computers.

Efficient High Speed Compression Trees on Xilinx FPGAs

Peter Zipf, Martin Kumm, 2014, MBMV.

Pipelined compressor tree optimization using integer linear programming

Peter Zipf, Martin Kumm, M. Kumm, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2007, 2007 International Conference on Field-Programmable Technology.

Eine weiterentwickelte quasi-statische adiabatische Logikfamilie

Manfred Glesner, Clemens Schlachta, Peter Zipf, 2005, GI Jahrestagung.

Model-based hardware design based on compatible sets of isomorphic subgraphs

Bogdan Pasca, Peter Zipf, Martin Kumm, 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

Selected Papers from ReCoSoC 2008

Michael Hübner, Peter Zipf, Juan Manuel Moreno, 2009, Int. J. Reconfigurable Comput..

An infrastructure for distributed computing and context aware computing

Max Mühlhäuser, Manfred Glesner, Tudor Murgan, 2003 .

An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders

Manfred Glesner, Tudor Murgan, Mihail Petrov, 2003, VLSI-SOC.

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits

Peter Zipf, Martin Kumm, Patrick Sittel, 2017, MBMV.

Signal processing hardware for single-bunch manipulation

Peter Zipf, Martin Kumm, Harald Klingbeil, 2018 .

Multiple constant multiplication with ternary adders

Jens Willkomm, Peter Zipf, Martin Kumm, 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

Fly - A Modifiable Hardware Compiler

Philip Heng Wai Leong, Alberto García Ortiz, Manfred Glesner, 2002, FPL.

Towards an Automated Design of Application-specific Reconfigurable Logic

Manfred Glesner, Peter Zipf, 2006, Dynamically Reconfigurable Architectures.

Reconfigurable FIR filter using distributed arithmetic on FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Constant Matrix Multiplication with Ternary Adders

Peter Zipf, Martin Kumm, Patrick Sittel, 2018, 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

On the design of reconfigurable multipliers for integer and Galois field multiplication

Manfred Glesner, Peter Zipf, Jia Li, 2009, Microprocess. Microsystems.

An Efficient Softcore Multiplier Architecture for Xilinx FPGAs

Peter Zipf, Martin Kumm, Shahid Abbas, 2015, 2015 IEEE 22nd Symposium on Computer Arithmetic.

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs

Manfred Glesner, Peter Zipf, Markus Rullmann, 2009, 2009 International Conference on Field Programmable Logic and Applications.

FIR filter optimization for video processing on

Uwe Meyer-Baese, Peter Zipf, Diana Fanghänel, 2013 .

A scalable reconfiguration mechanism for fast dynamic reconfiguration

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2008, 2008 International Conference on Field-Programmable Technology.

Dynamically Reconfigurable Constant Multiplication on FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2014, MBMV.

2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013

Leandro Soares Indrusiak, Kartikeya Bhardwaj, Pravin S. Mane, 2013, Reconfigurable Communication-centric Systems-on-Chip.

Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system

Peter Zipf, Martin Kumm, Michael Kunz, 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

Design Concepts for a Dynamically ReconfigurableWireless Sensor Node

Manfred Glesner, Peter Zipf, Heiko Hinkelmann, 2006, First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06).

Current Status and Future Perspectives

Peter Zipf, Manfred Glesner, M. Glesner, 2004 .

IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003

Leandro Soares Indrusiak, Hans Eveking, Manfred Glesner, 2003, VLSI-SoC.

Application-specific reconfigurable processors.

Norbert Wehn, Manfred Glesner, Peter Zipf, 2008, FPL 2008.

Dynamically Reconfigurable Computing for Wireless Communication Systems

Peter Zipf, Manfred Glesner, Heiko Hinkelmann, 2007 .

A Framework for Teaching (Re)Configurable Architectures in Student Projects

Manfred Glesner, Peter Zipf, Thilo Pionteck, 2002, FPL.

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers

Peter Zipf, Martin Kumm, Philip H. W. Leong, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

An FPGA-Based Linear All-Digital Phase-Locked Loop

Peter Zipf, Martin Kumm, Harald Klingbeil, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An Integrated Model Bridging the Gap between Technology and Economy

Manfred Glesner, Peter Zipf, Stephan Bingemer, 2003, VLSI-SOC.

FPGA Based Tunable Digital Filtering for Closed Loop RF Control in Synchrotrons

Martin Kumm, Peter Zipf, Dieter Lens, 2014 .

A DOMAIN-SPECIFICDYNAMICALLY RECONFIGURABLEHARDWARE PLATFORM FOR WIRELESSSENSORNETWORKS

Manfred Glesner, Peter Zipf, 2007 .

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design

Peter Zipf, Martin Kumm, John Wickerson, 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications

Peter Zipf, Michael Kunz, Alexander Ostrowski, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Reconfigurable Constant Multiplication for FPGAs

Peter Zipf, Martin Kumm, Konrad Möller, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

System Design with Genetic Algorithms

Peter Zipf, Hans Wojtkowiak, Christine Bauer, 2000, FPL.

Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques

Leandro Soares Indrusiak, Manfred Glesner, Tudor Murgan, 2005, SAMOS.

Optimal and Heuristic Approaches to Modulo Scheduling with Rational Initiation Intervals in Hardware Synthesis

Peter Zipf, John Wickerson, Patrick Sittel, 2021 .

Towards Highly Automated Machine-Learning-Empowered Monitoring of Motor Test Stands

Peter Zipf, Ludwig Brabetz, Bernhard Sick, 2021, 2021 IEEE International Conference on Autonomic Computing and Self-Organizing Systems (ACSOS).