Bahram Rashidi

发表

A Novel VLSI design and implementation of ultra low power digital FIR Filter based on a new signed shift / add multiplier with multiplexer ( 2 To 1 ) by pass transistor logic

Bahram Rashidi, Majid Pourormazd, 2012 .

High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA

Bahram Rashidi, Bahram Rashidi, 2013, IET Signal Process..

Glitch-less hardware implementation of block ciphers based on an efficient glitch filter

Bahram Rashidi, 2022, Integr..

Design of a low-power and low-cost booth-shift/add multiplexer-based multiplier

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2014, 2014 22nd Iranian Conference on Electrical Engineering (ICEE).

A high-speed multiplexer-based fine-grain pipelined architecture for digital fuzzy logic controllers

Bahram Rashidi, Sayed Masoud Sayedi, S. Sayedi, 2015 .

An adaptive multi-objective optimization method for optimum design of distribution networks

Bahram Rashidi, Mohammad Abedini, Mohamad Mohamadi, 2020, Engineering Optimization.

Design and implementation of low power digital FIR filter based on low power multipliers and adders on xilinx FPGA

Bahram Rashidi, Bahman Rashidi, Majid Pourormazd, 2011, 2011 3rd International Conference on Electronics Computer Technology.

Flexible structures of lightweight block ciphers PRESENT, SIMON and LED

Bahram Rashidi, Bahram Rashidi, 2020, IET Circuits Devices Syst..

Efficient hardware implementations of point multiplication for binary Edwards curves

Bahram Rashidi, Bahram Rashidi, 2018, Int. J. Circuit Theory Appl..

Low-Cost and Fast Hardware Implementations of Point Multiplication on Binary Edwards Curves

Bahram Rashidi, Bahram Rashidi, 2018, Electrical Engineering (ICEE), Iranian Conference on.

A Survey on Hardware Implementations of Elliptic Curve Cryptosystems pdf

Bahram Rashidi, Bahram Rashidi, 2017, ArXiv.

High-speed hardware implementation of Gaussian normal basis inversion algorithm over F2m

Bahram Rashidi, Bahram Rashidi, 2017, Microelectron. J..

High-performance and high-speed implementation of polynomial basis Itoh-Tsujii inversion algorithm over GF(2 m )

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2017, IET Inf. Secur..

High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2016, Microelectron. J..

High‐throughput and flexible ASIC implementations of SIMON and SPECK lightweight block ciphers

Bahram Rashidi, Bahram Rashidi, 2019, Int. J. Circuit Theory Appl..

Efficient full data-path width and serialized hardware structures of SPONGENT lightweight hash function

Bahram Rashidi, Bahram Rashidi, 2021, Microelectron. J..

Flexible and high-throughput structures of Camellia block cipher for security of the Internet of Things

Bahram Rashidi, Bahram Rashidi, 2021, IET Comput. Digit. Tech..

Compact and efficient structure of 8-bit S-box for lightweight cryptography

Bahram Rashidi, Bahram Rashidi, 2021, Integr..

Lightweight 8‐bit S‐box and combined S‐box/S‐box−1 for cryptographic applications

Bahram Rashidi, Bahram Rashidi, 2021, Int. J. Circuit Theory Appl..

FPGA implementation of optimized the 64-bit RC5 encryption algorithm

Bahram Rashidi, Bahram Rashidi, 2012 .

An efficient and high-speed VLSI implementation of optimal normal basis multiplication over GF(2m)

Bahram Rashidi, Reza Rezaeian Farashahi, Sayed Masoud Sayedi, 2016, Integr..

Implementation of a High Speed Technique for Character Segmentation of License Plate Based on Thresholding Algorithm

Bahram Rashidi, Bahman Rashidi, Bahram Rashidi, 2012 .