L. Clement

Gate-All-Around technology: taking advantage of ballistic transport ?

G. Ghibaudo, G. Bidal, T. Skotnicki, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications

T. Ernst, S. Deleonibus, T. Skotnicki, 2007, 2007 IEEE International Electron Devices Meeting.

300 mm Multi Level Air Gap Integration for Edge Interconnect Technologies and Specific High Performance Applications

V. Arnal, L. Pain, A. Farcy, 2008, 2008 International Interconnect Technology Conference.

Folded fully depleted Bulk+ technology as a highly W-scaled planar solution

G. Ghibaudo, G. Bidal, T. Skotnicki, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications

G. Ghibaudo, G. Bidal, M. Rafik, 2008, 2008 Symposium on VLSI Technology.

High velocity Si-nanodot : A candidate for SRAM applications at 16nm node and below

G. Ghibaudo, G. Bidal, T. Skotnicki, 2006, 2009 Symposium on VLSI Technology.

A Breakthrough Electronic Lithography Process Through Si Layer for Self Aligning Gates in Planar Double-Gate Transistors for 32nm Node And Below

Nicolas Loubet, Romain Wacquez, M.-P. Samson, 2007 .

Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors

O. Faynot, G. Ghibaudo, A. Pofelski, 2013, 2013 Symposium on VLSI Technology.