J.B. Kuo

A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb four-way set-associative CMOS cache memory implemented by 1.8V 0.18µm foundry CMOS technology for low-voltage low-power VLSI system applications

J.B. Kuo, P.F. Lin, F. Wang, 2000, Proceedings of the 26th European Solid-State Circuits Conference.

Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology

J.B. Kuo, H.L.A. Chen, E.K.W. Loo, 2007, 2007 Canadian Conference on Electrical and Computer Engineering.

A low voltage CMOS load driver with the adiabatic and bootstrap techniques for low-power system applications

J.B. Kuo, H.P. Chen, 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability

J.B. Kuo, B. Wang, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Evolution of low-voltage CMOS digital VLSI circuits using bootstrap technique

J.B. Kuo, 2004, International Meeting for Future of Electron Devices, 2004..

Gate-level dual-threshold total power optimization methodology (GDTPOM) principle for designing high-speed low-power SOC applications

R. Chen, J.B. Kuo, R. Liu, 2008, 2008 9th International Conference on Solid-State and Integrated-Circuit Technology.

Gate-Misalignment-Effect Related Capacitance Behavior of a 100nm Double-Gate FD SOI NMOS Device with n+/p+Poly Top/Bottom Gate

C.H. Hsu, J.B. Kuo, C.P. Yang, 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

MOS Pass transistor turn-off transient analysis

R.W. Dutton, B.A. Wooley, J.B. Kuo, 1986, IEEE Transactions on Electron Devices.

Low-Voltage Single-Phase Clocked Quasi-Adiabatic Pass-Gate Logic

J.B. Kuo, M. Syrzycki, E.K. Loo, 2007, 2007 Canadian Conference on Electrical and Computer Engineering.