Michael Papamichael

发表

Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing

James C. Hoe, Eric S. Chung, Michael Papamichael, 2012, FPGA '12.

DELPHI: a framework for RTL-based architecture design evaluation using DSENT models

Chen Sun, James C. Hoe, Vladimir Stojanovic, 2015, 2015 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS).

HPC on FPGA clouds: 3D FFTs and implications for molecular dynamics

Chen Yang, Jiayi Sheng, Martin C. Herbordt, 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

Thread Cluster Memory Scheduling

Mor Harchol-Balter, Onur Mutlu, Michael Papamichael, 2011, IEEE Micro.

Nautilus: Fast automated IP design space search using guided genetic algorithms

James C. Hoe, Michael Papamichael, Peter A. Milder, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Serving DNNs in Real Time at Datacenter Scale with Project Brainwave

Hari Angepat, Derek Chiou, Alessandro Forin, 2018, IEEE Micro.

Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

Mor Harchol-Balter, Onur Mutlu, Michael Papamichael, 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

The CONNECT Network-on-Chip Generator

James C. Hoe, Michael Papamichael, 2015, Computer.

CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs

James C. Hoe, Michael Papamichael, J. Hoe, 2012, FPGA '12.

Cross-platform FPGA accelerator development using CoRAM and CONNECT

James C. Hoe, Eric S. Chung, Michael Papamichael, 2013, FPGA '13.

Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor

Eric S. Chung, Michael Papamichael, Gabriel Weisz, 2019, IEEE Micro.

A cloud-scale acceleration architecture

Hari Angepat, Derek Chiou, Eric S. Chung, 2016, MICRO 2016.

Configurable Clouds

Hari Angepat, Derek Chiou, Eric S. Chung, 2017, IEEE Micro.

ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs

Babak Falsafi, James C. Hoe, Eriko Nurvitadhi, 2009, TRETS.

Towards automatic customization of interconnect and memory in the CoRAM abstraction (abstract only)

Eric S. Chung, Michael Papamichael, 2013, FPGA '13.

A cloud-scale acceleration architecture

Hari Angepat, Derek Chiou, Eric S. Chung, 2016, 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

A Configurable Cloud-Scale DNN Processor for Real-Time AI

Eric S. Chung, Michael Papamichael, Gabriel Weisz, 2018, 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA).

ShrinkWrap: Compiler-Enabled Optimization and Customization of Soft Memory Interconnects

Eric S. Chung, Michael Papamichael, 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

Fast scalable FPGA-based Network-on-Chip simulation models

Michael Papamichael, Michael Papamichael, 2011, Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011).

Agile Co-Design for a Reconfigurable Datacenter

Hari Angepat, Derek Chiou, Eric S. Chung, 2016, FPGA.

Prototyping Efficient Interprocessor Communication Mechanisms

Dionisios N. Pnevmatikatos, Michael Papamichael, Vassilis Papaefstathiou, 2007, 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation.

FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations

James C. Hoe, Onur Mutlu, Michael Papamichael, 2011, Proceedings of the Fifth ACM/IEEE International Symposium.