T. Nozomu

发表

An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead

Togawa Nozomu, Yanagisawa Masao, Kawamura Kazushi, 2013 .

A pipeline architecture optimization algorithm for SIMD-type processor core synthesis

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2006 .

Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2014 .

Speeding-up Exact and Fast L1 Cache Configuration Simulation based on FIFO Replacement Policy

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2010 .

A non-volatile memory writing reduction method based on state encoding limiting maximum Hamming distance

Togawa Nozomu, Yanagisawa Masao, Kimura Shinji, 2013 .

High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2009 .

An Energy-efficient ASIP Synthesis Method Using Scratchpad Memory and Code Placement Optimization

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2011 .

A Quantitative Criterion of Gate-Level Netlist Vulnerability

Togawa Nozomu, Yanagisawa Masao, Shi Youhua, 2015 .

A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures

Togawa Nozomu, Yanagisawa Masao, Terada Kotaro, 2016 .

The role of System and Signal Processing Subsociety -- Offering Effective Information of Research Groups and The Subsociety

Takai Shigemasa, Aikawa Naoyuki, Togawa Nozomu, 2019 .

A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures

Togawa Nozomu, Yanagisawa Masao, Igawa Koki, 2014 .

A Parallel Hardware Engine for Generating Deformed Maps

Togawa Nozomu, Yanagisawa Masao, Ohtsuki Tatsuo, 2008 .