Vijay Sundararajan

发表

Synthesis of low power CMOS VLSI circuits using dual supply voltages

Keshab K. Parhi, Vijay Sundararajan, 1999, DAC '99.

A novel multiply multiple accumulator component for low power PDSP design

Keshab K. Parhi, Vijay Sundararajan, 2000, 2000 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.00CH37100).

Optimal power allocation for sum capacity of a slotted three-cell system

Zukang Shen, Vikram Chandrasekhar, Vijay Sundararajan, 2008, 2008 IEEE International Conference on Acoustics, Speech and Signal Processing.

Reducing bus transition activity by limited weight coding with codeword slimming

Keshab K. Parhi, Vijay Sundararajan, 2000, ACM Great Lakes Symposium on VLSI.

Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems

Keshab K. Parhi, Vijay Sundararajan, 2003, IEEE Trans. Signal Process..

A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 2004, TODE.

Minflotransit: min-cost flow based transistor sizing tool

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 2000, Proceedings 37th Design Automation Conference.

A wavelet-domain algorithm for denoising in the presence of noise outliers

Keshab K. Parhi, Michalis E. Zervakis, Vijay Sundararajan, 1997, Proceedings of International Conference on Image Processing.

Data transmission over a bus with peak-limited transition activity

Keshab K. Parhi, Vijay Sundararajan, K. Parhi, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Vector processing of wavelet coefficients for robust image denoising

Keshab K. Parhi, Michalis E. Zervakis, Vijay Sundararajan, 2001, Image Vis. Comput..

Low power gate resizing of combinational circuits by buffer-redistribution

Keshab K. Parhi, Vijay Sundararajan, 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

Marsh:min-area retiming with setup and hold constraints

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

Synthesis of low power folded programmable coefficient FIR digital filters

Keshab K. Parhi, Vijay Sundararajan, K. Parhi, 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

Low power synthesis of dual threshold voltage CMOS VLSI circuits

Keshab K. Parhi, Vijay Sundararajan, 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

Gate Sizing

Vijay Sundararajan, 2016, Encyclopedia of Algorithms.

Synthesis of folded, pipelined architectures for multi-dimensional multirate systems

Keshab K. Parhi, Vijay Sundararajan, 1998, Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98 (Cat. No.98CH36181).

Energy efficient signaling in deep submicron CMOS technology

Keshab K. Parhi, Hannu Tenhunen, Imed Ben Dhaou, 2001, Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design.

Gate Sizing

Vijay Sundararajan, 2008, Encyclopedia of Algorithms.

Energy efficient signaling in DSM CMOS technology

Keshab K. Parhi, Hannu Tenhunen, Imed Ben Dhaou, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Fast and exact transistor sizing based on iterative relaxation

Keshab K. Parhi, Sachin S. Sapatnekar, Vijay Sundararajan, 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..