Aneesh Nainani

Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain

Krishna C. Saraswat, Ashish Pal, Aneesh Nainani, 2013, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

Understanding device impact of line edge/width roughness in frequency domain

Peng Xie, He Ren, Huixiong Dai, 2013, Advanced Lithography.

Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

Udayan Ganguly, Saurabh Lodha, Aneesh Nainani, 2014, IEEE Transactions on Electron Devices.

Impact of fixed charge on metal-insulator-semiconductor barrier height reduction

H.-S. Philip Wong, Krishna C. Saraswat, Aneesh Nainani, 2011 .

on-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained $ \hbox{Si}_{0.5}\hbox{Ge}_{0.5}$ Quantum-Well pMOSFET Along $ \langle \hbox{110} \rangle$ and $\langle \hbox{100} \rangle$ Channel Directions

Leonard Franklin Register, Raj Jammy, Aneesh Nainani, 2011, IEEE Transactions on Electron Devices.

InxGa1-xSb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design

Krishna C. Saraswat, Mario G. Ancona, J. B. Boos, 2011 .

High-Mobility Ge N-MOSFETs and Mobility Degradation Mechanisms

Duygu Kuzum, Aneesh Nainani, Tejas Krishnamohan, 2011, IEEE Transactions on Electron Devices.

Engineering of strained III–V heterostructures for high hole mobility

Mario G. Ancona, Masaharu Kobayashi, Brian R. Bennett, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

on-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained Quantum-Well pMOSFET Along and Channel Directions

Raj Jammy, Aneesh Nainani, Prashant Majhi, 2011 .