S.M. Reddy

On testing of interconnect open defects in combinational logic circuits with stems of large fanout

I. Pomeranz, Huaxing Tang, S.M. Reddy, 2002, Proceedings. International Test Conference.

On determining scan flip-flops in partial-scan designs

S.M. Reddy, D.H. Lee, S. Reddy, 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values

S.M. Reddy, S. Kajihara, K.K. Saluja, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

Don't-care identification on specific bits of test patterns

I. Pomeranz, S.M. Reddy, S. Kajihara, 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.