M. Jeeradit

Semi-Custom High-Speed Datapath Design Using Commericial ASIC Design Tools

M. Horowitz, A. Amirkhany, M. Jeeradit, 2007 .

Emerging Applications : Networking Applications

M. Jeeradit, Janani Ravi, John Kim, 2003 .

Compressing extended program traces using value predictors

Martin Burtscher, Metha Jeeradit, Martin Burtscher, 2003, 2003 12th International Conference on Parallel Architectures and Compilation Techniques.

Intent-leveraged optimization of analog circuits via homotopy

Jaeha Kim, Mark Horowitz, Metha Jeeradit, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Leveraging designer's intent: A path toward simpler analog CAD tools

ByongChan Lim, Jaeha Kim, Mark Horowitz, 2009, 2009 IEEE Custom Integrated Circuits Conference.

A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications

A. Amirkhany, B.W. Garlepp, J. Savoj, 2008, IEEE Journal of Solid-State Circuits.